Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I

Abstract

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250-nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248 nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

arXiv comment21 pagers, 21 figures, 4 tables, 61 references. This work was presented at Applied Superconductivity Conference, ASC 2020 Virtual Conference, Oct. 24 - Nov. 7, 2020

References in corpus (14)

• Architectural considerations in the design of a superconducting quantum annealing processor
• Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
• Superconductor Digital Electronics: Scalability and Energy Efficiency Issues
• Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits
• A scalable control system for a superconducting adiabatic quantum optimization processor
• A scalable readout system for a superconducting adiabatic quantum optimization system
• Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2
• Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers
• Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories
• AC-Biased Shift Registers as Fabrication Process Benchmark Circuits and Flux Trapping Diagnostic Tool
• Superconductor Electronics Fabrication Process with MoN${}_x$ Kinetic Inductors and Self-Shunted Josephson Junctions
• Deep Sub-Micron Stud-Via Technology for Superconductor VLSI Circuits
• Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions
• Diffusion stop-layers for superconducting integrated circuits and qubits with Nb-based Josephson junctions

Cited by in corpus (8)

• Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
• Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations
• Vulnerability to Parameter Spread in Josephson Traveling-Wave Parametric Amplifiers
• Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
• Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers
• Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes
• Contemporary implementations of spiking bio-inspired neural networks
• Disentangling superconductor and dielectric microwave losses in sub-micron $\mathrm{Nb}$/$\mathrm{TEOS}-\mathrm{Si}{\mathrm{O}}_2$ interconnects using a multi-mode microstrip resonator