Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Abstract

Arrays of Vortex Transitional (VT) memory cells with functional density up to $1Mbit/c{m}^2$ have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-$\mu A/\mu m^2$ MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied $168\mu m^2$, resulting in an over $0.5Mbit/c{m}^2$ functional density. Then, we reduced the cell area down to $99\mu m^2$ (corresponding to over $0.9Mbit/c{m}^2$ functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, $J_c$ of $600\mu A/\mu m^2$ and eliminating shunt resistors. The fabricated high-$J_c$ memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-$J_c$ junctions similar to variable thickness bridges.

9 pages, 10 figures, 1 Table, 49 references. Submitted to IEEE Transactions on Applied Superconductivity on October 30, 2018; in revised version on February 22, 2019. Presented at Applied Superconductivity Conference ASC 2018, 28 Oct.- 2 Nov. 2018, Seattle, WA, USA; paper 4EPo-1D

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