Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations

Abstract

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% in a very wide range of parameters. They can be used for superconductor integrated circuit design and calibration of numerical inductance extractors. Measurements were done using circuits fabricated in fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, known as the SFQ5ee and SC1 processes developed at MIT Lincoln Laboratory for superconductor electronics. Mutual inductance decreases exponentially with distance between striplines and as a second power of the distance between microstrips, strongly depends on magnetic field penetration depths in superconducting ground planes, whereas superconducting properties of the signal traces are practically immaterial. Weak dependence of mutual inductance on the linewidth of superconducting wires indicates that area of superconducting flux transformers - the essential component of all digital circuits using ac power, superconducting qubits, and sensor arrays - scales poorly with the linewidth, putting a predictable upper limit on the integration scale of such circuits.

35 pages, 28 figures, 2 tables, 86 references

References in corpus (6)

• Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers
• Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories
• Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I
• SFQ bias for SFQ digital circuits
• Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
• Propagation of Picosecond Pulses on Superconducting Transmission Line Interconnects

Cited by in corpus (7)

• Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
• Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
• Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers
• Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes
• Disentangling superconductor and dielectric microwave losses in sub-micron $\mathrm{Nb}$/$\mathrm{TEOS}-\mathrm{Si}{\mathrm{O}}_2$ interconnects using a multi-mode microstrip resonator
• Kinetic inductance of superconducting nanostrips with turns
• Demonstration of Superconductor Shift Registers with Energy Dissipation Below Landauer's Thermodynamic Limit