253 citations · 1.6k across the 38 of their papers we have counts for
38 papers
Elimination of Flux Trapping in Superconducting Circuits in Ambient Magnetic Fields
Rohan T. Kapur, Alex Wynn, Sergey K. Tolpygo +10
Superconductor digital electronics and quantum computing with superconducting qubits are promising next-generation computing technologies. When cooled down or operated in the prese…
Mitigation of Magnetic Flux Trapping in Superconducting Electronics Using Moats
Rohan T. Kapur, Sergey K. Tolpygo, Alex Wynn +7
Magnetic flux (vortex) trapping remains a major obstacle to very large scale integration in superconducting electronics. Moats -- etched regions in circuit layers placed in ground…
Demonstration of Superconductor Shift Registers with Energy Dissipation Below Landauer's Thermodynamic Limit
Sergey K. Tolpygo, Evan B. Golden, Vasili K. Semenov
We study energy dissipation and propagation of information encoded by Josephson vortices in two types of circular shift register: a) a uniform register composed of sections of disc…
Magnetic flux imaging in a 3D superconductor integrated circuit
Tong Ren, Andres Glatz, Boldizsar Jankó +3
We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the…
Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions
Sergey K. Tolpygo, Ravi Rastogi, David Kim +3
Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs…
Flux-trapping characterization for superconducting electronics using a cryogenic widefield N- diamond microscope
Rohan T. Kapur, Pauli Kehayias, Sergey K. Tolpygo +12
Magnetic flux trapping is a significant hurdle limiting the reliability and scalability of superconducting electronics, yet tools for imaging flux vortices remain slow or insensiti…
Development of a Neuromorphic Network Using BioSFQ Circuits
Evan B. Golden, Vasili K. Semenov, Sergey K. Tolpygo
Superconductor electronics (SCE) appear promising for low energy applications. However, the achieved and projected circuit densities are insufficient for direct competition with CM…
Extraction and Simulation of the Impact of Flux Trapping in Moats of AC-Biased Shift Registers
Scott E. Meninger, Sergey K. Tolpygo
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapp…
Characterization of Adiabatic Quantum-Flux-Parametrons in the MIT LL SFQ5ee+ Process
Sergey K. Tolpygo, Evan B. Golden, Christopher L. Ayala +4
Adiabatic quantum-flux-parametron (AQFP) logic is a proven energy-efficient superconductor technology for various applications. To address the scalability challenges, we investigat…
Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbN/Nb Junctions
Sergey K. Tolpygo, Ravi Rastogi, Terence Weir +2
To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existi…
Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
Sergey K. Tolpygo, Justin L. Mallek, Vladimir Bolkhovsky +5
To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of Josephson junctions (JJs) per chip, we developed a new fabricat…
BioSFQ circuit family for neuromorphic computing: Bridging digital and analog domains of superconductor technologies
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have…
Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers
Sergey K. Tolpygo
Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing ac power for logic cell excitation and clocking, and flux biasing, e.g., A…
Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +2
We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electron…
Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober
Joshua T. West, Arthur Kurlej, Alex Wynn +3
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including…
Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal trac…
A new family of bioSFQ logic/memory cells
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly…
Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I
Sergey. K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm an…
SFQ bias for SFQ digital circuits
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per squa…
Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories
Vasili K. Semenov, Yuri A. Polyakov, Sergey K. Tolpygo
Arrays of Vortex Transitional (VT) memory cells with functional density up to have been designed, fabricated, and successfully demonstrated. This progress is due to r…
Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +6
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-m…
Superconductor Electronics Fabrication Process with MoN Kinetic Inductors and Self-Shunted Josephson Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, D. E. Oates +6
Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm chi…
Ring Oscillators for Clocking Reversible Superconducting Circuits and Fabrication Process Benchmarking
Vasili K. Semenov, Yuri A. Polyakov, Sergey K. Tolpygo
Existing concepts of reversible superconducting circuits as well as demonstrated adiabatic circuits require three-phase bias/clock signals generated by room temperature sources. A…
Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +5
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junc…