Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers

Abstract

Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing ac power for logic cell excitation and clocking, and flux biasing, e.g., Adiabatic Quantum Flux Parametron (AQFP), Reciprocal Quantum Logic, superconducting sensor arrays, qubits, etc. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines and cross coupling between the adjacent transformers. The former sets the minimum line width and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size of transformers. As a result, there is a minimum linewidth ~100 nm which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependence of the AQFP number density on linewidth for various types of transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm^2. We propose an advanced fabrication process for a 10x increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material (Nb) deposited over a layer of high kinetic inductance material (e.g., NbN). Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low crosstalk.

18 pages, 18 figures, 45 references

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Cited by in corpus (2)

• Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
• Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes