164 citations · 568 across the 14 of their papers we have counts for
14 papers
Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)
Rabindra N. Das, Vladimir Bolkhovsky, Alex Wynn +9
Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) c…
Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
Sergey K. Tolpygo, Justin L. Mallek, Vladimir Bolkhovsky +5
To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of Josephson junctions (JJs) per chip, we developed a new fabricat…
BioSFQ circuit family for neuromorphic computing: Bridging digital and analog domains of superconductor technologies
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have…
Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +2
We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electron…
Low-Cost Superconducting Fan-Out with Cell I Ranking
Jennifer Volk, George Tzimpragos, Alex Wynn +2
Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CM…
Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal trac…
A new family of bioSFQ logic/memory cells
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly…
Fabrication of superconducting through-silicon vias
Justin L. Mallek, Donna-Ruth W. Yost, Danna Rosenberg +15
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic syst…
Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I
Sergey. K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm an…
SFQ bias for SFQ digital circuits
Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo
Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per squa…
Comparison of Dielectric Loss in Titanium Nitride and Aluminum Superconducting Resonators
Alexander Melville, Greg Calusine, Wayne Woods +8
Lossy dielectrics are a significant source of decoherence in superconducting quantum circuits. In this report, we model and compare the dielectric loss in bulk and interfacial diel…
Solid-state qubits integrated with superconducting through-silicon vias
Donna-Ruth W. Yost, Mollie E. Schwartz, Justin Mallek +14
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may re…
Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +6
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-m…
Determining interface dielectric losses in superconducting coplanar waveguide resonators
Wayne Woods, Greg Calusine, Alexander Melville +6
Superconducting quantum computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLS) in bulk and interfacial dielectrics. Under…