activity
20182021
most citedPlanarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

29 citations · 46 across the 2 of their papers we have counts for

collaborators

7 papers

quant-ph202117 cited

Fabrication of superconducting through-silicon vias

Justin L. Mallek, Donna-Ruth W. Yost, Danna Rosenberg +15

Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic syst…

cond-mat.supr-con2021

Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I

Sergey. K. Tolpygo, Evan B. Golden, Terence J. Weir +1

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm an…

cond-mat.supr-con2020

SFQ bias for SFQ digital circuits

Vasili K. Semenov, Evan B. Golden, Sergey K. Tolpygo

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per squa…

quant-ph2020

Comparison of Dielectric Loss in Titanium Nitride and Aluminum Superconducting Resonators

Alexander Melville, Greg Calusine, Wayne Woods +8

Lossy dielectrics are a significant source of decoherence in superconducting quantum circuits. In this report, we model and compare the dielectric loss in bulk and interfacial diel…

quant-ph2019

Solid-state qubits integrated with superconducting through-silicon vias

Donna-Ruth W. Yost, Mollie E. Schwartz, Justin Mallek +14

As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may re…

cond-mat.supr-con201929 cited

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +6

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-m…