253 citations · 788 across the 16 of their papers we have counts for
16 papers
Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions
Sergey K. Tolpygo, Ravi Rastogi, David Kim +3
Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs…
Reflection-less filter for superconducting quantum circuits
Jessica Kedziora, Eric Q. Bui, Alec Yen +4
Protecting superconducting quantum circuits from non-ideal return loss, including out-of-band circulator behavior and enhancing the performance of broadband quantum-limited amplifi…
Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbN/Nb Junctions
Sergey K. Tolpygo, Ravi Rastogi, Terence Weir +2
To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existi…
Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
Sergey K. Tolpygo, Justin L. Mallek, Vladimir Bolkhovsky +5
To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of Josephson junctions (JJs) per chip, we developed a new fabricat…
Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +2
We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electron…
Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations
Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal trac…
Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I
Sergey. K. Tolpygo, Evan B. Golden, Terence J. Weir +1
Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm an…
Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +6
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-m…
Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions
Sergey K. Tolpygo, Vladimir Bolkhovsky, Ravi Rastogi +5
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junc…
Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2
Sergey K. Tolpygo, Vladimir Bolkhovsky, Scott Zarr +5
We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their ba…
Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
Sergey K. Tolpygo, Vladimir Bolkhovsky, T. J. Weir +4
We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ)…
Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits
Sergey K. Tolpygo, Vladimir Bolkhovsky, Terence J. Weir +3
A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is…
Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers
Sergey K. Tolpygo, Vladimir Bolkhovsky, T. J. Weir +4
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and micro…
Deep Sub-Micron Stud-Via Technology for Superconductor VLSI Circuits
Sergey K. Tolpygo, V. Bolkhovsky, T. Weir +3
A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large…
Shadow evaporation of epitaxial Al/Al2O3/Al tunnel junctions on sapphire utilizing an inorganic bilayer mask
Paul B. Welander, Vladimir Bolkhovsky, Terence J. Weir +2
This letter describes a new inorganic shadow mask that has been employed for the evaporation of all-epitaxial Al/Al2O3/Al superconducting tunnel junctions. Organic resists that are…
Sub-micrometer epitaxial Josephson junctions for quantum circuits
Jeffrey S. Kline, Michael R. Vissers, Fabio C. S. da Silva +11
We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yieldin…