Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

Abstract

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2\,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4\,K and 4.2\,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77\,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

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• Rapid cryogenic characterisation of 1024 integrated silicon quantum dots
• Revised theoretical limit of subthreshold swing in field-effect transistors
• A Review on Quantum Computing: Qubits, Cryogenic Electronics and Cryogenic MOSFET Physics
• Method for efficient large-scale cryogenic characterization of CMOS technologies