SpinQ: Compilation strategies for scalable spin-qubit architectures

Abstract

Despite NISQ devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring solutions on such devices. In this work, we discuss the unique mapping challenges of a scalable crossbar architecture with shared control and introduce SpinQ, the first native compilation framework for scalable spin-qubit architectures. At the core of SpinQ is the Integrated Strategy that addresses the unique operational constraints of the crossbar while considering compilation scalability and obtaining a O(n) computational complexity. To evaluate the performance of SpinQ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping techniques that could increase algorithm success rates on this architecture and potentially inspire further research on quantum circuit mapping for other scalable spin-qubit architectures.

18 pages, 16 figures

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Cited by in corpus (7)

• Near-Term Spin-Qubit Architecture Design via Multipartite Maximally-Entangled States
• beSnake: A routing algorithm for scalable spin-qubit architectures
• Lightcone Bounds for Quantum Circuit Mapping via Uncomplexity
• Compiling the surface code to crossbar spin qubit architectures
• Improving Figures of Merit for Quantum Circuit Compilation
• Limitations of the $g$-tensor formalism of semiconductor spin qubits
• Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture