Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture

Abstract

In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.

Accepted to ISCAS 25

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