The impact of stochastic incorporation on atomic-precision Si:P arrays

Abstract

Scanning tunneling microscope lithography can be used to create nanoelectronic devices in which dopant atoms are precisely positioned in a Si lattice within $\sim$1 nm of a target position. This exquisite precision is promising for realizing various quantum technologies. However, a potentially impactful form of disorder is due to incorporation kinetics, in which the number of P atoms that incorporate into a single lithographic window is manifestly uncertain. We present experimental results indicating that the likelihood of incorporating into an ideally written three-dimer single-donor window is $63\pm 10\%$ for room-temperature dosing, and corroborate these results with a model for the incorporation kinetics. Nevertheless, further analysis of this model suggests conditions that might raise the incorporation rate to near-deterministic levels. We simulate bias spectroscopy on a chain of comparable dimensions to the array in our yield study, indicating that such an experiment may help confirm the inferred incorporation rate.

20 pages, 13 figures

References in corpus (8)

• KMCLib: A general framework for lattice kinetic Monte Carlo (KMC) simulations
• STM characterization of the Si-P heterodimer
• Spin-lattice relaxation times of single donors and donor clusters in silicon
• Extended Hubbard model for mesoscopic transport in donor arrays in silicon
• Full configuration interaction simulations of exchange-coupled donors in silicon using multi-valley effective mass theory
• CMOS Platform for Atomic-Scale Device Fabrication
• All-optical lithography process for contacting atomically-precise devices
• Interface-induced heavy-hole/light-hole splitting of acceptors in silicon

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• Roadmap on Atomic-scale Semiconductor Devices
• Near-Surface Electrical Characterisation of Silicon Electronic Devices Using Focused keV Ions
• Hole in one: Pathways to deterministic single-acceptor incorporation in Si(100)-2$\times$1
• Uncovering anisotropic effects of electric high-moment dipoles on the tunneling current in $\delta$-layer tunnel junctions
• Influence of imperfections on tunneling rate in $\delta$-layer junctions
• Probing the Atomic Arrangement of Sub-Surface Dopants in a Silicon Quantum Device Platform