Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures

Abstract

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high-fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology we advance 300 mm epitaxial wafers manufactured in an industrial CMOS fab to a record electron mobility of (3.9$\pm$0.6)$\times$10${}^5$ cm${}^2$\slash Vs and percolation density of (6.9$\pm$0.4)$\times$10${}^{10}$ cm${}^{-2}$, representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information and because of the simplicity of assembly, low-cost, yet versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

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Cited by in corpus (18)

• Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives
• Probing single electrons across 300 mm spin qubit wafers
• Reducing charge noise in quantum dots by using thin silicon quantum wells
• Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots
• Low charge noise quantum dots with industrial CMOS manufacturing
• Overcoming I/O bottleneck in superconducting quantum computing: multiplexed qubit control with ultra-low-power, base-temperature cryo-CMOS multiplexer
• Germanium wafers for strained quantum wells with low disorder
• Semiconductor materials stacks for quantum dot spin qubits
• Low disorder and high valley splitting in silicon
• Millikelvin temperature cryo-CMOS multiplexer for scalable quantum device characterisation
• Wafer-scale low-disorder 2DEG in ${}^{28}$Si/SiGe without an epitaxial Si cap
• Effect of quantum Hall edge strips on valley splitting in silicon quantum wells
• Scalable on-chip multiplexing of silicon single and double quantum dots
• Valley splitting in silicon from the interference pattern of quantum oscillations
• Near-Term Spin-Qubit Architecture Design via Multipartite Maximally-Entangled States
• Reducing disorder in Ge quantum wells by using thick SiGe barriers
• Overhead in Quantum Circuits with Time-Multiplexed Qubit Control
• A Thermally Modulated SINIS Trasconductance Amplifier