Can Tunnel Transistors Scale Below 10nm?

Abstract

The main promise of tunnel FETs (TFETs) is to enable supply voltage ($V_{DD}$) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing $V_{DD}$ and channel length ($L_{ch}$) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high perfor]mance TFET with both low V${}_{DD}$ ($\sim$0.2V) and small $L_{ch}$ ($\sim$6nm). In this work, it is shown that scaling TFETs in general requires scaling down the bandgap $E_g$ and scaling up the effective mass $m^{\ast }$ for high performance. Quantitatively, a channel material with an optimized bandgap ($E_g\sim 1.2q{V}_{DD}[eV]$) and an engineered effective mass ($m{\ast }^{-1}\sim 40V_{DD}^{2.5}[m_0^{-1}]$) makes both $V_{DD}$ and $L_{ch}$ scaling feasible with the scaling rule of $L_{ch}/V_{DD}=30nm/V$ for $L_{ch}$ from 15nm to 6nm and corresponding $V_{DD}$ from 0.5V to 0.2V.

4 pages, 5 figures

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Cited by in corpus (9)

• Few-layer Phosphorene: An Ideal 2D Material For Tunnel Transistors
• Saving Moore's Law Down To 1nm Channels With Anisotropic Effective Mass
• Thickness Engineered Tunnel Field-Effect Transistors based on Phosphorene
• Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET
• Design Rules for High Performance Tunnel Transistors from 2D Materials
• Sensitivity Challenge of Steep Transistors
• Combination of equilibrium and non-equilibrium carrier statistics into an atomistic quantum transport model for tunneling hetero-junctions
• Dramatic Impact of Dimensionality on the Electrostatics of PN Junctions
• Impact of Dimensionality on PN Junctions