Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors
arXiv:1404.0020 · doi:10.1109/TED.2014.2309651
Abstract
We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technology
to appear in IEEE Transactions on Electron Devices (2014)
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Cited by in corpus (4)
- Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors
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- Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors
- Contact resistance extraction of graphene FET technologies based on individual device characterization