Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors

Abstract

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.

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Cited by in corpus (6)

• Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors
• Exploiting ambipolarity in graphene field-effect transistors for novel designs on high-frequency analog electronics
• A Scalable Compact Model for the Static Drain Current of Graphene FETs
• Graphene on Silicon Hybrid Field-Effect Transistors
• The gate tunable 2D pn junction driven out-of-equilibrium
• Bias-dependent intrinsic RF thermal noise modeling and characterization of single layer graphene FETs