Contact resistance extraction of graphene FET technologies based on individual device characterization

Abstract

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-effect transistors from different technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift-diffusion-like transport in graphene devices under certain bias conditions. In contrast to other available approaches for contact resistance extraction of graphene transistors, the practical methods used here do not require either the fabrication of dedicated test structures or internal device phenomena characterization. The methodologies are evaluated with simulation-based data and applied to fabricated devices. The extracted values are close to the ones obtained with other more intricate methodologies. Bias-dependent contact and channel resistances studies, bias-dependent high-frequency performance studies and contact engineering studies are enhanced and evaluated by the extracted contact resistance values.

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Cited by in corpus (9)

• Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors
• Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors
• A small-signal GFET equivalent circuit considering an explicit contribution of contact resistances
• An extraction method for mobility degradation and contact resistance of graphene transistors
• Unveiling the impact of the bias-dependent charge neutrality point on graphene-based multi-transistor applications
• A Scalable Compact Model for the Static Drain Current of Graphene FETs
• Accuracy of Y-function methods for parameters extraction of two-dimensional FETs across different technologies
• Contact resistance assessment and high-frequency performance projection of black phosphorus field-effect transistor technologies
• Bias-dependent intrinsic RF thermal noise modeling and characterization of single layer graphene FETs