On-chip Integration of Si/SiGe-based Quantum Dots and Switched-capacitor Circuits

Abstract

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

References in corpus (22)

• Quantum Computation with Quantum Dots
• Surface codes: Towards practical large-scale quantum computation
• Single-shot read-out of an individual electron spin in a quantum dot
• A >99.9%-fidelity quantum-dot spin qubit with coherence limited by charge noise
• Single-shot readout of an electron spin in silicon
• A programmable two-qubit quantum processor in silicon
• Interfacing spin qubits in quantum dots and donors - hot, dense and coherent
• Quantum CNOT Gate for Spins in Silicon
• Electrical control of a long-lived spin qubit in a Si/SiGe quantum dot
• Silicon CMOS architecture for a spin-based quantum computer
• Strong spin-photon coupling in silicon
• A Crossbar Network for Silicon Quantum Dot Qubits
• Benchmarking Gate Fidelities in a Si/SiGe Two-Qubit Device
• A CMOS dynamic random access architecture for radio-frequency readout of quantum devices
• Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices
• Multiplexed Charge-locking Device for Large Arrays of Quantum Devices
• Integration of on-chip field-effect transistor switches with dopantless Si/SiGe quantum dots for high-throughput testing
• A Cryogenic Interface for Controlling Many Qubits
• Photon-induced entanglement of distant mesoscopic SQUID rings
• Conditional dispersive readout of a CMOS quantum dot via an integrated transistor circuit
• A sparse spin qubit array with integrated control electronics
• Fabrication of quantum dots in undoped Si/Si${}_{0.8}$Ge${}_{0.2}$ heterostructures using a single metal-gate layer

Cited by in corpus (8)

• CMOS-based cryogenic control of silicon quantum circuits
• Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives
• Spiderweb array: A sparse spin-qubit array
• How to wire a 1000-qubit trapped ion quantum computer
• Memristor-based cryogenic programmable DC sources for scalable in-situ quantum-dot control
• RFSoC-based radio-frequency reflectometry in gate-defined bilayer graphene quantum devices
• Second Quantization: Gating a Quantum Dot Through the Sequential Removal of Single Electrons from a Nanoscale Floating Gate
• Density dependence of the excitation gaps in an undoped Si/SiGe double-quantum-well heterostructure