Fabrication of quantum dots in undoped Si/Si${}_{0.8}$Ge${}_{0.2}$ heterostructures using a single metal-gate layer

Abstract

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for \revEdit{their} potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30\%. Here we report the fabrication and low-temperature characterization of quantum dots in Si/Si${}_{0.8}$Ge${}_{0.2}$ heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 $\mu$m increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratio used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. The device uses only a single metal-gate layer, greatly simplifying device design and fabrication.

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• Quantum Computation with Quantum Dots
• Electron transport through double quantum dots
• Silicon Quantum Electronics
• Electron Spin-Relaxation Times of Phosphorus Donors in Silicon
• Quantum control and process tomography of a semiconductor quantum dot hybrid qubit
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Cited by in corpus (5)

• Algorithm for automated tuning of a quantum dot into the single-electron regime
• Single and Double Hole Quantum Dots in Strained Ge/SiGe Quantum Wells
• Quantum dots with split enhancement gate tunnel barrier control
• On-chip Integration of Si/SiGe-based Quantum Dots and Switched-capacitor Circuits
• Spectroscopy of multi-electrode tunnel barriers