Optimum High-k Oxide for the Best Performance of Ultra-scaled Double-Gate MOSFETs

Abstract

A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as $\mathrm{Si}{\mathrm{O}}_2$, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness (${\mathrm{T}}_{\mathrm{OX}}$) for each gate stack, including $\mathrm{Si}{\mathrm{O}}_2$ interface layer and one high-k material. For the same EOT, $\mathrm{A}{\mathrm{l}}_2{\mathrm{O}}_3$ (k=9) over 3 $\mathring{\mathrm{A}}$ $\mathrm{Si}{\mathrm{O}}_2$ provides the best performance, while for $\mathrm{Hf}{\mathrm{O}}_2$ (k=20) and $\mathrm{L}{\mathrm{a}}_2{\mathrm{O}}_3$ (k=30), $\mathrm{Si}{\mathrm{O}}_2$ thicknesses should be 5 $\mathring{\mathrm{A}}$ and 7 $\mathring{\mathrm{A}}$, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

5 pages

References in corpus (1)

• Tunnel Field-Effect Transistors in 2D Transition Metal Dichalcogenide Materials

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