Clean BN encapsulated 2D FETs with lithography compatible contacts

Abstract

Device passivation through ultraclean hexagonal BN encapsulation is proven one of the most effective ways for constructing high-quality devices with atomically thin semiconductors that preserves the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility in straightforwardly integrating lithography defined contacts into BN encapsulated 2D FETs, giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. Electronic characterization on FETs consisting of WSe${}_2$ and MoS${}_2$ channels reveals an extremely low scanning hysteresis of ca. 2 mV on average, a low density of interfacial charged impurity of ca. $10^{11}$cm${}^{-2}$, and generally high charge mobilities over $1000$cm${}^2\cdot$V${}^{-1}\cdot$s${}^{-1}$ at low temperatures. The overall high device qualities verify the viability in directly integrating lithography defined contacts into BN encapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.

17 pages, 4 figures

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Cited by in corpus (3)

• Enhancement of Carrier Mobility in Semiconductor Nanostructures by Carrier Distribution Engineering
• Intrinsic Electronic Properties of BN Encapsulated, van der Waals Contacted MoSe${}_2$ FETs
• A nanogapped hysteresis-free field-effect transistor