21 citations · 26 across the 18 of their papers we have counts for
18 papers
Unveiling the Scaling Potential of Drain Merge through Active (DMtA) in CFETs: Breaking the Super-Via Bottlenecks and Unlocking New PPA Boosters
Jingru Jiang, Haoran Lu, Kairong Guo +11
Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scalin…
MacroAgent: Regularity-Aware Macro Legalization with LLM-Agent-Designed Contour Algorithms
Jiaxi Jiang, Xufeng Yao, Yuxuan Zhao +5
Macros constitute a large part of the core area in modern very large-scale integration (VLSI) designs. Moreover, macro positions have a significant impact on the final quality of r…
Kimi K3: Open Frontier Intelligence
Kimi Team, Tongtong Bai, Yifan Bai +398
We introduce Kimi K3, a 2.8T parameter Mixture-of-Experts model with 104 billion activated parameters, native vision capabilities, and a 1-million-token context window. Kimi K3 is…
GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
Xin Xin, Jincheng Lou, Junhui Li +11
Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large la…
DataPrep-Bench: Benchmarking LLMs as Training Data Preparators
Hao Liang, Qifeng Cai, Yibo Lin +11
The quality of training data fundamentally determines the capabilities of large language models (LLMs), yet no unified benchmark exists to measure how well LLMs, agents, and data-c…
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Haoyi Zhang, Weijian Fan, Xiaohan Gao +3
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Haoyi Zhang, Kairong Guo, Bojie Zhang +2
Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…
LEGO: An LLM Skill-Based Front-End Design Generation Platform
Jincheng Lou, Ruohan Xu, Jiecheng Ma +3
Existing LLM-based EDA agents are often isolated task-specific systems. This leads to repeated engineering effort and limited reuse of successful design and debugging strategies. W…
Evolution of Optimization Algorithms for Global Placement via Large Language Models
Xufeng Yao, Jiaxi Jiang, Yuxuan Zhao +3
Optimization algorithms are widely employed to tackle complex problems, but designing them manually is often labor-intensive and requires significant expertise. Global placement is…
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
Jingchen Zhu, Chenhao Xue, Yiqi Chen +13
The emergence of the large language model~(LLM) poses an exponential growth of demand for computation throughput, memory capacity, and communication bandwidth. Such a demand growth…
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design
Bingyang Liu, Haoyi Zhang, Xiaohan Gao +5
Analog layout design heavily involves interactive processes between humans and design tools. Electronic Design Automation (EDA) tools for this task are usually designed to use scri…
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
Lei Chen, Yiqi Chen, Zhufei Chu +36
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Haoyi Zhang, Jiahao Song, Xiaohan Gao +4
Analog Computing-in-Memory (ACIM) is an emerging architecture to perform efficient AI edge computing. However, current ACIM designs usually have unscalable topology and still heavi…
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction
Yuxiang Zhao, Zhuomin Chai, Xun Jiang +3
IR drop on the power delivery network (PDN) is closely related to PDN's configuration and cell current consumption. As the integrated circuit (IC) design is growing larger, dynamic…
Analytical Heterogeneous Die-to-Die 3D Placement with Macros
Yuxuan Zhao, Peiyu Liao, Siting Liu +3
This paper presents an innovative approach to 3D mixed-size placement in heterogeneous face-to-face (F2F) bonded 3D ICs. We propose an analytical framework that utilizes a dedicate…
Post-Layout Simulation Driven Analog Circuit Sizing
Xiaohan Gao, Haoyi Zhang, Siyuan Ye +6
Post-layout simulation provides accurate guidance for analog circuit design, but post-layout performance is hard to be directly optimized at early design stages. Prior work on anal…
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration
Peiyu Liao, Yuxuan Zhao, Dawei Guo +2
In this paper, we present a new analytical 3D placement framework with a bistratal wirelength model for F2F-bonded 3D ICs with heterogeneous technology nodes based on the electrost…
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction
Zuodong Zhang, Renjie Wei, Meng Li +3
With the rapid advancements of deep learning in recent years, hardware accelerators are continuously deployed in more and more safety-critical applications such as autonomous drivi…