The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
arXiv:2403.07257 · doi:10.1007/s11432-024-4155-7
Abstract
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an AI4EDA approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This paper argues for a paradigm shift from AI4EDA towards AI-native EDA, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, RTL designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-native philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound shift-left in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.
arXiv commentThe authors are ordered alphabetically. Contact: qxu@cse[dot]cuhk[dot]edu[dot]hk, gluo@pku[dot]edu[dot]cn, yuan.mingxuan@huawei[dot]com
References in corpus (43)
- A Simple Framework for Contrastive Learning of Visual Representations
- Learning Transferable Visual Models From Natural Language Supervision
- Exploring the Limits of Transfer Learning with a Unified Text-to-Text Transformer
- On the Opportunities and Risks of Foundation Models
- Momentum Contrast for Unsupervised Visual Representation Learning
- Gemini: A Family of Highly Capable Multimodal Models
- High-Resolution Image Synthesis with Latent Diffusion Models
- CodeBERT: A Pre-Trained Model for Programming and Natural Languages
- The Dawn of LMMs: Preliminary Explorations with GPT-4V(ision)
- egg: Fast and Extensible Equality Saturation
- FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
- Ithemal: Accurate, Portable and Fast Basic Block Throughput Estimation using Deep Neural Networks
- A Full-Stack Search Technique for Domain Optimized Deep Learning Accelerators
- Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
- ChipGPT: How far are we from natural language hardware design
- ChipNeMo: Domain-Adapted LLMs for Chip Design
- AutoChip: Automating HDL Generation Using LLM Feedback
- VerilogEval: Evaluating Large Language Models for Verilog Code Generation
- Using LLMs to Facilitate Formal Verification of RTL
- RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
- Unleashing the Potential of LLMs for Quantum Computing: A Study in Quantum Architecture Design
- Datapath Combinational Equivalence Checking With Hybrid Sweeping Engines and Parallelization
- BetterV: Controlled Verilog Generation with Discriminative Guidance
- AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
- LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
- GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
- Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
- OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
- On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators
- SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design
- DiLA: Enhancing LLM Tool Learning with Differential Logic Layer
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks
- DeepGate2: Functionality-Aware Circuit Representation Learning
- HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation
- Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned
- Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
- NPS: A Framework for Accurate Program Sampling Using Graph Neural Network
- Learning Generalizable Program and Architecture Representations for Performance Modeling
- DeepGate3: Towards Scalable Circuit Representation Learning
- Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data