95 citations · 134 across the 21 of their papers we have counts for
23 papers
FABO: Agent-Guided Discovery of Joint Breakpoint Optimization for Timing-Driven Routing Trees
Shang Liu, Wenji Fang, Jing Wang +3
The topology of a routing tree determines how a multi-pin net branches and shares physical wire, directly affecting wirelength, congestion, capacitance, and delay. We study a centr…
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
Yao Lu, Zhicheng Guo, Qijun Zhang +4
Advanced 3D and 3.5D IC packaging significantly improves integration density but elevates thermal management challenges due to cross-layer heat coupling and complex cooling structu…
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
Wenkai Li, Yuchao Wu, Ziyan Guo +4
Accurate power analysis is critical in VLSI design, as it directly impacts power optimization strategies. However, traditional approaches are often hindered by the substantial runt…
CircuitProver: Agentic Lean 4 Theorem Proving with Reusable Circuit Proof Library for Hardware Verification
Ziyi Yang, Wenji Fang, Chen Chen +2
Modern integrated circuits (ICs) are becoming increasingly complex, making functional verification a major bottleneck. The dominant hardware formal verification methodology, model…
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Ziyan Guo, Wenji Fang, Wenkai Li +3
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive field…
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jing Wang, Shang Liu, Wenji Fang +3
LLM-based RTL generation and reasoning is a promising direction for hardware design automation. High-quality benchmarks are critical infrastructure for tracking progress in this di…
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Yuchao Wu, Wenji Fang, Jing Wang +3
Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-inte…
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
Wenji Fang, Yao Lu, Shang Liu +5
Recent advances in large language models (LLMs) have sparked growing interest in automatic RTL optimization for better performance, power, and area (PPA). However, existing methods…
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization
Yao Lu, Shang Liu, Hangan Zhou +3
The rapid progress of artificial intelligence increasingly relies on efficient integrated circuit (IC) design. Recent studies have explored the use of large language models (LLMs)…
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Shang Liu, Jing Wang, Wenji Fang +1
In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain.…
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Wenkai Li, Yao Lu, Wenji Fang +3
Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, tradi…
Profile-Guided Temporal Prefetching
Mengming Li, Qijun Zhang, Yichuan Gao +4
Temporal prefetching shows promise for handling irregular memory access patterns, which are common in data-dependent and pointer-based data structures. Recent studies introduced on…
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Wenji Fang, Shang Liu, Jing Wang +1
The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent…
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Wenji Fang, Wenkai Li, Shang Liu +3
Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Exist…
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
Wenji Fang, Jing Wang, Yao Lu +2
The success of foundation AI has motivated the research of circuit foundation models, which are customized to assist the integrated circuit (IC) design process. However, existing p…
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Zhiyuan Yan, Wenji Fang, Mengming Li +4
Assertion-based verification (ABV) is a critical method to ensure logic designs comply with their architectural specifications. ABV requires assertions, which are generally convert…
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
Lei Chen, Yiqi Chen, Zhufei Chu +36
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Wenji Fang, Shang Liu, Hongce Zhang +1
In digital IC design, compared with post-synthesis netlists or layouts, the early register-transfer level (RTL) stage offers greater optimization flexibility for both designers and…
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Wenji Fang, Mengming Li, Min Li +4
Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural langua…
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Mengming Li, Wenji Fang, Qijun Zhang +1
The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are cra…
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
Shang Liu, Wenji Fang, Yao Lu +3
The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. Howe…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…