172 citations · 275 across the 16 of their papers we have counts for
17 papers
AttentionCap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction
Jiechen Huang, Hector R. Rodriguez, Dingcheng Yang +3
As capacitance extraction accuracy of rule-based pattern matching becomes difficult to sustain at advanced nodes, a growing trend emerges to develop deep-learning-based 2D capacita…
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction
Zhixiong Di, Runzhe Tao, Lin Chen +2
Packing is a required step in a typical FPGA CAD flow. It has high impacts to the performance of FPGA placement and routing. Early prediction of packing results can guide design op…
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
Zhixiong Di, Runzhe Tao, Jing Mai +2
Multi-die FPGAs are crucial components in modern computing systems, particularly for high-performance applications such as artificial intelligence and data centers. Super long line…
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
Jing Mai, Jiarui Wang, Zhixiong Di +3
This paper proposes OpenPARF, an open-source placement and routing framework for large-scale FPGA designs. OpenPARF is implemented with the deep learning toolkit PyTorch and suppor…
HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction
Yuxiang Zhao, Zhuomin Chai, Yibo Lin +2
Accurate early congestion prediction can prevent unpleasant surprises at the routing stage, playing a crucial character in assisting designers to iterate faster in VLSI design cycl…
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization
Jing Mai, Jiarui Wang, Zhixiong Di +1
When modern FPGA architecture becomes increasingly complicated, modern FPGA placement is a mixed optimization problem with multiple objectives, including wirelength, routability, t…
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
Zhuomin Chai, Yuxiang Zhao, Yibo Lin +3
The electronic design automation (EDA) community has been actively exploring machine learning (ML) for very large-scale integrated computer-aided design (VLSI CAD). Many studies ex…
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Bowen Wang, Guibao Shen, Dong Li +7
Precise congestion prediction from a placement solution plays a crucial role in circuit placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation f…
Concurrent CPU-GPU Task Programming using Modern C++
Tsung-Wei Huang, Yibo Lin
In this paper, we introduce Heteroflow, a new C++ library to help developers quickly write parallel CPU-GPU programs using task dependency graphs. Heteroflow leverages the power of…
Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview
Junchi Yan, Xianglong Lyu, Ruoyu Cheng +1
Placement and routing are two indispensable and challenging (NP-hard) tasks in modern chip design flows. Compared with traditional solvers using heuristics or expert-well-designed…
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++
Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo +1
Pipeline is a fundamental parallel programming pattern. Mainstream pipeline programming frameworks count on data abstractions to perform pipeline scheduling. This design is conveni…
Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System
Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin +1
Taskflow aims to streamline the building of parallel and heterogeneous applications using a lightweight task graph-based approach. Taskflow introduces an expressive task graph prog…
Towards a Theoretical Understanding of Hashing-Based Neural Nets
Yibo Lin, Zhao Song, Lin F. Yang
Parameter reduction has been an important topic in deep learning due to the ever-increasing size of deep neural network models and the need to train and run them on resource limite…
OpenMPL: An Open Source Layout Decomposer
Wei Li, Yuzhe Ma, Qi Sun +4
Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decompositi…
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection
Yibo Lin, Meng Li, Yuki Watanabe +4
Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to…
Learning Long Term Dependencies via Fourier Recurrent Units
Jiong Zhang, Yibo Lin, Zhao Song +1
It is a known fact that training recurrent neural networks for tasks that have long term dependencies is challenging. One of the main reasons is the vanishing or exploding gradient…
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao +1
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography…