activity
20232026
most citedThe Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models

21 citations · 26 across the 18 of their papers we have counts for

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Showing 2026Show all

8 papers · 1 filter

cond-mat.mes-hall2026

Unveiling the Scaling Potential of Drain Merge through Active (DMtA) in CFETs: Breaking the Super-Via Bottlenecks and Unlocking New PPA Boosters

Jingru Jiang, Haoran Lu, Kairong Guo +11

Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scalin…

cs.LG2026

MacroAgent: Regularity-Aware Macro Legalization with LLM-Agent-Designed Contour Algorithms

Jiaxi Jiang, Xufeng Yao, Yuxuan Zhao +5

Macros constitute a large part of the core area in modern very large-scale integration (VLSI) designs. Moreover, macro positions have a significant impact on the final quality of r…

cs.CL2026

Kimi K3: Open Frontier Intelligence

Kimi Team, Tongtong Bai, Yifan Bai +398

We introduce Kimi K3, a 2.8T parameter Mixture-of-Experts model with 104 billion activated parameters, native vision capabilities, and a 1-million-token context window. Kimi K3 is…

cs.AI2026

GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure

Xin Xin, Jincheng Lou, Junhui Li +11

Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large la…

cs.LG2026

DataPrep-Bench: Benchmarking LLMs as Training Data Preparators

Hao Liang, Qifeng Cai, Yibo Lin +11

The quality of training data fundamentally determines the capabilities of large language models (LLMs), yet no unified benchmark exists to measure how well LLMs, agents, and data-c…

cs.AR2026

PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation

Haoyi Zhang, Weijian Fan, Xiaohan Gao +3

Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…

cs.LG2026

FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

Haoyi Zhang, Kairong Guo, Bojie Zhang +2

Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…

cs.AI2026

LEGO: An LLM Skill-Based Front-End Design Generation Platform

Jincheng Lou, Ruohan Xu, Jiecheng Ma +3

Existing LLM-based EDA agents are often isolated task-specific systems. This leads to repeated engineering effort and limited reuse of successful design and debugging strategies. W…