Going beyond copper: wafer-scale synthesis of graphene on sapphire

Abstract

The adoption of graphene in electronics, optoelectronics and photonics is hindered by the difficulty in obtaining high quality material on technologically-relevant substrates, over wafer-scale sizes and with metal contamination levels compatible with industrial requirements. To date, the direct growth of graphene on insulating substrates has proved to be challenging, usually requiring metal-catalysts or yielding defective graphene. In this work, we demonstrate a metal-free approach implemented in commercially available reactors to obtain high-quality monolayer graphene on c-plane sapphire substrates via chemical vapour deposition (CVD). We identify via low energy electron diffraction (LEED), low energy electron microscopy (LEEM) and scanning tunneling microscopy (STM) measurements the Al-rich reconstruction root31R9 of sapphire to be crucial for obtaining epitaxial graphene. Raman spectroscopy and electrical transport measurements reveal high-quality graphene with mobilities consistently above 2000 cm2/Vs. We scale up the process to 4-inch and 6-inch wafer sizes and demonstrate that metal contamination levels are within the limits for back-end-of-line (BEOL) integration. The growth process introduced here establishes a method for the synthesis of wafer-scale graphene films on a technologically viable basis.

arXiv comment15 main text pages, 4 main text figures, 13 supplementary information pages, 12 supplementary figures, 3 supplementary tables

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Cited by in corpus (7)

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• Fermi velocity renormalization in graphene probed by terahertz time-domain spectroscopy
• Assessment of wafer-level transfer techniques of graphene with respect to semiconductor industry requirements
• Plasma induced surface modification of sapphire and its influence on graphene grown by PECVD
• Excitons in epitaxially grown WS2 on Graphene: a nanometer-resolved EELS and DFT study
• Thermal stability of monolayer $W{S}_2$ in BEOL conditions