Substrate Gating of Contact Resistance in Graphene Transistors

Abstract

Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it was observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this letter, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. Our study indicates that the engineering of metal- graphene interface is a crucial step towards reducing the contact resistance for high performance graphene transistors.

5 pages, 4 figures

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• Model of the Electrostatics and Tunneling Current of Metal-Graphene Junctions and Metal-Insulator-Graphene Heterostructures
• A physics based model of gate tunable metal-graphene contact resistance benchmarked against experimental data
• Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions
• Local transport measurements on epitaxial graphene
• Carrier density modulation in graphene underneath Ni electrode