4.5k citations
Counting papers with at most 25 authors, so collaboration author lists do not stand in for the people here.
- ETH ZurichCH46 papers
- University of BolognaIT11 papers
- Haute Ecole Arc IngénierieCH4 papers
- HES-SO ArcCH4 papers
- IBM Research - ZurichCH4 papers
- HES-SO University of Applied Sciences and Arts Western SwitzerlandCH3 papers
- National Institute for Materials ScienceJP3 papers
- École Polytechnique Fédérale de LausanneCH2 papers
- Fondazione Bruno KesslerIT2 papers
- Purdue University West LafayetteUS2 papers
- Rice UniversityUS2 papers
- University of Alabama in HuntsvilleUS2 papers
6 papers · 1 filter
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Matteo Perotti, Matheus Cavalcante, Nils Wistoff +3
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips,…
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini +4
Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-con…
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
Andreas Kurth, Wolfgang Rönninger, Thomas Benz +4
On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of compo…
Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
Florian Zaruba, Fabian Schuiki, Torsten Hoefler +1
Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emergi…
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI
Matheus Cavalcante, Fabian Schuiki, Florian Zaruba +2
In this paper, we present Ara, a 64-bit vector processor based on the version 0.5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX FD-SOI technology. Ara's…
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
Florian Zaruba, Luca Benini
The open-source RISC-V ISA is gaining traction, both in industry and academia. The ISA is designed to scale from micro-controllers to server-class processors. Furthermore, openness…