190 citations · 1.5k across the 53 of their papers we have counts for
55 papers
Improving Autonomous Nano-drones Performance via Automated End-to-End Optimization and Deployment of DNNs
Vlad Niculescu, Lorenzo Lamberti, Francesco Conti +2
The evolution of energy-efficient ultra-low-power (ULP) parallel processors and the diffusion of convolutional neural networks (CNNs) are fueling the advent of autonomous driving n…
TrainDeeploy: Hardware-Accelerated Parameter-Efficient Fine-Tuning of Small Transformer Models at the Extreme Edge
Run Wang, Victor J. B. Jung, Philip Wiese +3
On-device tuning of deep neural networks enables long-term adaptation at the edge while preserving data privacy. However, the high computational and memory demands of backpropagati…
Safe-NEureka: a Hybrid Modular Redundant DNN Accelerator for On-board Satellite AI Processing
Riccardo Tedeschi, Luigi Ghionda, Alessandro Nadalini +5
Low Earth Orbit (LEO) constellations are revolutionizing the space sector, with on-board Artificial Intelligence (AI) becoming pivotal for next-generation satellites. AI accelerati…
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators
Chi Zhang, Luca Colagrande, Renzo Andri +6
Multi-Head Attention (MHA) is a critical computational kernel in transformer-based AI models. Emerging scalable tile-based accelerator architectures integrate increasing numbers of…
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
Gamze İslamoğlu, Luca Bertaccini, Arpan Suravi Prasad +3
Fast and energy-efficient low-bitwidth floating-point (FP) arithmetic is essential for Artificial Intelligence (AI) systems. Microscaling (MX) standardized formats have recently em…
VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers
Run Wang, Gamze Islamoglu, Andrea Belano +4
While Transformers are dominated by Floating-Point (FP) Matrix-Multiplications, their aggressive acceleration through dedicated hardware or many-core programmable systems has shift…
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti +11
Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumpt…
Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience
Francesco Conti, Angelo Garofalo, Davide Rossi +2
Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-sou…
A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU
Andrea Belano, Yvan Tortorella, Angelo Garofalo +3
Transformer-based generative Artificial Intelligence (GenAI) models achieve remarkable results in a wide range of fields, including natural language processing, computer vision, an…
Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs
Severin Bochem, Victor J. B. Jung, Arpan Prasad +2
Contextual Artificial Intelligence (AI) based on emerging Transformer models is predicted to drive the next technology revolution in interactive wearable devices such as new-genera…
Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Alberto Dequino, Alessio Carpegna, Davide Nadalini +4
Rehearsal-based Continual Learning (CL) has been intensely investigated in Deep Neural Networks (DNNs). However, its application in Spiking Neural Networks (SNNs) has not been expl…
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Josse Van Delm, Maarten Vandersteegen, Alessio Burrello +5
Optimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these SoC…
Multi-resolution Rescored ByteTrack for Video Object Detection on Ultra-low-power Embedded Systems
Luca Bompani, Manuele Rusci, Daniele Palossi +2
This paper introduces Multi-Resolution Rescored Byte-Track (MR2-ByteTrack), a novel video object detection framework for ultra-low-power embedded processors. This method reduces th…
Optimizing the Deployment of Tiny Transformers on Low-Power MCUs
Victor J. B. Jung, Alessio Burrello, Moritz Scherer +2
Transformer networks are rapidly becoming SotA in many fields, such as NLP and CV. Similarly to CNN, there is a strong push for deploying Transformer models at the extreme edge, ul…
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
Arpan Suravi Prasad, Moritz Scherer, Francesco Conti +9
Extended reality (XR) applications are Machine Learning (ML)-intensive, featuring deep neural networks (DNNs) with millions of weights, tightly latency-bound (10-20 ms end-to-end),…
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge
Georg Rutishauser, Francesco Conti, Luca Benini
Mixed-precision quantization, where a deep neural network's layers are quantized to different precisions, offers the opportunity to optimize the trade-offs between model size, late…
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks
Alessandro Nadalini, Georg Rutishauser, Alessio Burrello +5
The emerging trend of deploying complex algorithms, such as Deep Neural Networks (DNNs), increasingly poses strict memory and energy efficiency requirements on Internet-of-Things (…
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi +19
Recent trends in deep learning (DL) have made hardware accelerators essential for various high-performance computing (HPC) applications, including image classification, computer vi…
Reduced Precision Floating-Point Optimization for Deep Neural Network On-Device Learning on MicroControllers
Davide Nadalini, Manuele Rusci, Luca Benini +1
Enabling On-Device Learning (ODL) for Ultra-Low-Power Micro-Controller Units (MCUs) is a key step for post-deployment adaptation and fine-tuning of Deep Neural Network (DNN) models…
Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays
Mattia Sinigaglia, Luca Bertaccini, Luca Valente +5
Emerging applications in the IoT domain require ultra-low-power and high-performance end-nodes to deal with complex near-sensor-data analytics. Domains such as audio, radar, and St…
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing
Francesco Conti, Gianna Paulin, Angelo Garofalo +7
Emerging Artificial Intelligence-enabled Internet-of-Things (AI-IoT) System-on-a-Chip (SoC) for augmented reality, personalized healthcare, and nano-robotics need to run many diver…
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training
Angelo Garofalo, Yvan Tortorella, Matteo Perotti +5
On-chip DNN inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy and flexibility requirements. Heterogeneous clusters are promising solut…
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
Michael Rogenmoser, Yvan Tortorella, Davide Rossi +2
Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying sol…
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge
Matteo Risso, Alessio Burrello, Francesco Conti +6
Neural Architecture Search (NAS) is quickly becoming the go-to approach to optimize the structure of Deep Learning (DL) models for complex tasks such as Image Classification or Obj…