activity
20162026
most citedThe Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology

428 citations · 4.5k across the 191 of their papers we have counts for

collaborators

220 papers

eess.IV2026★ 31 cited

Improving Autonomous Nano-drones Performance via Automated End-to-End Optimization and Deployment of DNNs

Vlad Niculescu, Lorenzo Lamberti, Francesco Conti +2

The evolution of energy-efficient ultra-low-power (ULP) parallel processors and the diffusion of convolutional neural networks (CNNs) are fueling the advent of autonomous driving n…

cs.CV2026

Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System

Lorenzo Lamberti, Manuele Rusci, Marco Fariselli +2

In this paper, we present the first (to the best of our knowledge) demonstration of a low-power MCU-based edge device for Automatic License Plate Recognition (ALPR). The design lev…

eess.SY2024

H-Watch: An Open, Connected Platform for AI-Enhanced COVID19 Infection Symptoms Monitoring and Contact Tracing

Tommaso Polonelli, Lukas Schulthess, Philipp Mayer +2

The novel COVID-19 disease has been declared a pandemic event. Early detection of infection symptoms and contact tracing are playing a vital role in containing COVID-19 spread. As…

cs.RO2024

Tiny-PULP-Dronets: Squeezing Neural Networks for Faster and Lighter Inference on Multi-Tasking Autonomous Nano-Drones

Lorenzo Lamberti, Vlad Niculescu, Michał Barcis +4

Pocket-sized autonomous nano-drones can revolutionize many robotic use cases, such as visual inspection in narrow, constrained spaces, and ensure safer human-robot interaction due…

cs.AR2023★ 8 cited

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters

Jie Chen, Igor Loi, Eric Flamand +3

High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) has r…

cs.AR2023

PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge

Vikram Jain, Matheus Cavalcante, Nazareno Bruschi +6

Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packe…