428 citations · 4.5k across the 191 of their papers we have counts for
37 papers · 1 filter
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra
Paul Scheffler, Florian Zaruba, Fabian Schuiki +2
Sparse-dense linear algebra is crucial in many domains, but challenging to handle efficiently on CPUs, GPUs, and accelerators alike; multiplications with sparse formats like CSR an…
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect
Matheus Cavalcante, Samuel Riedel, Antonio Pullini +1
A key challenge in scaling shared-L1 multi-core clusters towards many-core (more than 16 cores) configurations is to ensure low-latency and efficient access to the L1 memory. In th…
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti +2
This work introduces lightweight extensions to the RISC-V ISA to boost the efficiency of heavily Quantized Neural Network (QNN) inference on microcontroller-class cores. By extendi…
CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration with Better-than-Binary Energy Efficiency
Moritz Scherer, Georg Rutishauser, Lukas Cavigelli +1
We present a 3.1 POp/s/W fully digital hardware accelerator for ternary neural networks. CUTIE, the Completely Unrolled Ternary Inference Engine, focuses on minimizing non-computat…
Binarization Methods for Motor-Imagery Brain-Computer Interface Classification
Michael Hersche, Luca Benini, Abbas Rahimi
Successful motor-imagery brain-computer interface (MI-BCI) algorithms either extract a large number of handcrafted features and train a classifier, or combine feature extraction an…
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes
Hayate Okuhara, Ahmed Elnaqib, Davide Rossi +4
As the Internet-of-Things (IoT) applications become more and more pervasive, IoT end nodes are requiring more and more computational power within a few mW of power envelope, couple…
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini +3
Low bit-width Quantized Neural Networks (QNNs) enable deployment of complex machine learning models on constrained devices such as microcontrollers (MCUs) by reducing their memory…
PsPIN: A high-performance low-power architecture for flexible in-network compute
Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu +5
The capacity of offloading data and control tasks to the network is becoming increasingly important, especially if we consider the faster growth of network speed when compared to C…
Robust High-dimensional Memory-augmented Neural Networks
Geethan Karunaratne, Manuel Schmuck, Manuel Le Gallo +4
Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapti…
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
Andreas Kurth, Wolfgang Rönninger, Thomas Benz +4
On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of compo…
A transprecision floating-point cluster for efficient near-sensor data analytics
Fabio Montagna, Stefan Mach, Simone Benatti +5
Recent applications in the domain of near-sensor computing require the adoption of floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this…
Leveraging Automated Mixed-Low-Precision Quantization for tiny edge microcontrollers
Manuele Rusci, Marco Fariselli, Alessandro Capotondi +1
The severe on-chip memory limitations are currently preventing the deployment of the most accurate Deep Neural Network (DNN) models on tiny MicroController Units (MCUs), even if le…
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
Florian Zaruba, Fabian Schuiki, Luca Benini
Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a gene…
Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI
Alfio Di Mauro, Davide Rossi, Antonio Pullini +2
The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected by environmental temperature and process variations. Mitigating the effect of th…
Memory-Latency-Accuracy Trade-offs for Continual Learning on a RISC-V Extreme-Edge Node
Leonardo Ravaglia, Manuele Rusci, Alessandro Capotondi +5
AI-powered edge devices currently lack the ability to adapt their embedded inference models to the ever-changing environment. To tackle this issue, Continual Learning (CL) strategi…
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node
Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone +2
Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise, making aggressive voltage scaling attractive as a power-saving technique for both logic and SR…
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22 INL
Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang +2
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lowe…
FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
Stefan Mach, Fabian Schuiki, Florian Zaruba +1
The slowdown of Moore's law and the power wall necessitates a shift towards finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need ci…
Improving Memory Utilization in Convolutional Neural Network Accelerators
Petar Jokic, Stephane Emery, Luca Benini
While the accuracy of convolutional neural networks has achieved vast improvements by introducing larger and deeper network architectures, also the memory footprint for storing the…
Robustifying the Deployment of tinyML Models for Autonomous mini-vehicles
Miguel de Prado, Manuele Rusci, Romain Donze +4
Standard-size autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to low-power systems deployed o…
Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes
Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro +5
A wide range of Internet of Things (IoT) applications require powerful, energy-efficient and flexible end-nodes to acquire data from multiple sources, process and distill the sense…
TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition with Short Range Radars
Moritz Scherer, Michele Magno, Jonas Erb +3
This work proposes a low-power high-accuracy embedded hand-gesture recognition algorithm targeting battery-operated wearable devices using low power short-range RADAR sensors. A 2D…
Automated Design Space Exploration for optimised Deployment of DNN on Arm Cortex-A CPUs
Miguel de Prado, Andrew Mundy, Rabia Saeed +3
The spread of deep learning on embedded devices has prompted the development of numerous methods to optimise the deployment of deep neural networks (DNN). Works have mainly focused…
EEG-TCNet: An Accurate Temporal Convolutional Network for Embedded Motor-Imagery Brain-Machine Interfaces
Thorir Mar Ingolfsson, Michael Hersche, Xiaying Wang +3
In recent years, deep learning (DL) has contributed significantly to the improvement of motor-imagery brain-machine interfaces (MI-BMIs) based on electroencephalography(EEG). While…