203 citations
Counting papers with at most 25 authors, so collaboration author lists do not stand in for the people here.
- G. Sirakoulis2 profiles20 · h 36
- Nikolaos Vasileiadis13 · h 9
- P. Dimitrakis3 profiles13 · h 25
- A. Mavropoulis11 · h 3
- P. Normand2 profiles10 · h 29
- A. Adamatzky8 · h 51
- Alexandros Gazis7 · h 9
- P. Efraimidis7 · h 20
- B. Papadopoulos6 · h 19
- G. Dimitrakopoulos6 · h 19
- Kyriakos Papadopoulos6 · h 9
- N. M. Glykos6 · h 18
- University of CyprusCY36 papers
- Fermi National Accelerator LaboratoryUS33 papers
- University of IoanninaGR33 papers
- Istanbul Technical UniversityTR32 papers
- At BristolGB31 papers
- Boğaziçi UniversityTR31 papers
- Boston UniversityUS31 papers
- Brown UniversityUS31 papers
- California Institute of TechnologyUS31 papers
- Carnegie Mellon UniversityUS31 papers
- Cornell UniversityUS31 papers
- Cukurova UniversityTR31 papers
5 papers · 1 filter
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos +1
Deep Learning (DL) has achieved unprecedented success in various application domains. Meanwhile, model pruning has emerged as a viable solution to reduce the footprint of DL models…
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating
C. Peltekis, D. Filippas, G. Dimitrakopoulos +1
Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local…
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
D. Filippas, C. Peltekis, G. Dimitrakopoulos +1
The acceleration of deep-learning kernels in hardware relies on matrix multiplications that are executed efficiently on Systolic Arrays (SA). To effectively trade off deep-learning…
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
C. Peltekis, D. Filippas, G. Dimitrakopoulos +2
Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performan…
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
Minas Dasygenis, Erik Brockmeyer, Bart Durinck +3
The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-la…