29 citations · 79 across the 45 of their papers we have counts for
49 papers
LEAN: Loss-Engineered Modulation of the Model Weight-Sensitivity Distribution for Efficient, Error-Tolerant Neural Networks
Habibur Rahaman, Swarup Bhunia
The weights of a trained network do not have uniform sensitivity to model accuracy: the 1% most sensitive weights carry about a fifth of the damage a bit flip can do. This distribu…
BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
Habibur Rahaman, Swastik Bhattacharya, Sanjay Das +2
Deep Neural Networks (DNNs) are integral to many safety critical systems, yet they remain highly vulnerable to bit-flip attacks (BFAs), where a few memory level perturbations can d…
CITADEL: CWE-Guided Insertion of Hardware Trojans via Analysis of DFG-Enabled LLMs
Jayanth Thangellamudi, Raghul Saravanan, Sudipta Paria +2
The increasing sophistication of Hardware Trojans (HTs) and system-level vulnerabilities poses significant risks to modern integrated circuits. However, constructing realistic HT s…
Security-Enhanced Seed-Based Weight Quantization for Large Language Models
Qiuyu Ren, Sudipta Paria, Aritra Dasgupta +1
Large language models (LLMs) incur substantial storage, memory-bandwidth and energy costs, motivating compact weight representations. Existing seed-based compression methods recons…
Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights
Sudipta Paria, Aritra Dasgupta, Raghul Saravanan +3
Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verifica…
(A)iSpy: Parasitic Trojans for Machine Learning Infrastructure
Habibur Rahaman, Qipan Xu, Zafaryab Haider +3
Modern machine learning (ML) pipelines depend heavily on third party libraries for graph compilation and hardware acceleration. While current practices audit data and model artifac…
An Automated Framework for Generating Stealthy Cell-Embedded Hardware Trojans
Raghul Saravanan, Sudipta Paria, Sai Manoj P D +1
Hardware Trojans (HTs) pose significant threats across the Integrated Circuit (IC) design lifecycle because they can be inserted by untrusted entities at different stages under the…
FrequencyFormer: A Co-Designed Sensor-to-Processor Pipeline for Frequency-Domain Vision Transformer Inference
Chengwei Zhou, Ovishake Sen, Xuming Chen +5
Deploying vision transformers (ViTs) on sensor-edge systems is limited not only by on-device compute, but also by the energy and bandwidth required to transmit high-dimensional ima…
Characterizing the Impact of NVFP4 Quantization for Low-Power Edge AI Deployment
Ovishake Sen, Venkata Nithin Kamineni, Daniel Lobo +3
Energy-efficient neural-network inference at the edge requires reducing arithmetic cost, memory traffic, computation energy, and storage overhead while maintaining acceptable accur…
LASH: Adaptive Semantic Hybridization for Black-Box Jailbreaking of Large Language Models
Abdullah Al Nomaan Nafi, Fnu Suya, Swarup Bhunia +1
Jailbreak attacks expose a persistent gap between the intended safety behavior of aligned large language models and their behavior under adversarial prompting. Existing automated m…
CIPHR: Cryptography Inspired IP Protection through Fine-Grain Hardware Redaction
Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
Hardware intellectual property (IP) in the globalized integrated circuit (IC) supply chain is exposed to a wide range of confidentiality and integrity attacks by untrusted third-pa…
COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
Mahmudul Hasan, Sudipta Paria, Swarup Bhunia +1
Commercial Off-The-Shelf (COTS) hardware, such as microprocessors, are widely adopted in system design due to their ability to reduce development time and cost compared to custom s…
HAMLOCK: HArdware-Model LOgically Combined attacK
Sanskar Amgain, Daniel Lobo, Atri Chatterjee +2
The growing use of third-party hardware accelerators (e.g., FPGAs, ASICs) for deep neural networks (DNNs) introduces new security vulnerabilities. Conventional model-level backdoor…
Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +2
Hardware Fuzzing emerged as one of the crucial techniques for finding security flaws in modern hardware designs by testing a wide range of input scenarios. One of the main challeng…
DASH: A Meta-Attack Framework for Synthesizing Effective and Stealthy Adversarial Examples
Abdullah Al Nomaan Nafi, Habibur Rahaman, Zafaryab Haider +4
Numerous techniques have been proposed for generating adversarial examples in white-box settings under strict Lp-norm constraints. However, such norm-bounded examples often fail to…
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Tanzim Mahfuz, Sudipta Paria, Tasneem Suha +2
Microelectronic systems are widely used in many sensitive applications (e.g., manufacturing, energy, defense). These systems increasingly handle sensitive data (e.g., encryption ke…
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
Kshitij Raj, Atri Chatterjee, Patanjali SLPSK +2
Designing secure architectures for system-on-chip (SoC) platforms is a highly intricate and time-intensive task, often requiring months of development and meticulous verification.…
Secure and Storage-Efficient Deep Learning Models for Edge AI Using Automatic Weight Generation
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
Complex neural networks require substantial memory to store a large number of synaptic weights. This work introduces WINGs (Automatic Weight Generator for Secure and Storage-Effici…
LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta +2
Ensuring the security of modern System-on-Chip (SoC) designs poses significant challenges due to increasing complexity and distributed assets across the intellectual property (IP)…
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta +2
Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D hetero…
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +3
In the evolving landscape of integrated circuit (IC) design, the increasing complexity of modern processors and intellectual property (IP) cores has introduced new challenges in en…
Runtime Detection of Adversarial Attacks in AI Accelerators Using Performance Counters
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
Rapid adoption of AI technologies raises several major security concerns, including the risks of adversarial perturbations, which threaten the confidentiality and integrity of AI a…
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection
Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha +2
Hardware Trojans are malicious modifications in digital designs that can be inserted by untrusted supply chain entities. Hardware Trojans can give rise to diverse attack vectors su…
Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection
Aritra Dasgupta, Sudipta Paria, Christopher Sozio +2
Existing countermeasures for hardware IP protection, such as obfuscation, camouflaging, and redaction, aim to defend against confidentiality and integrity attacks. However, within…