29 citations · 79 across the 45 of their papers we have counts for
12 papers · 1 filter
HAMLOCK: HArdware-Model LOgically Combined attacK
Sanskar Amgain, Daniel Lobo, Atri Chatterjee +2
The growing use of third-party hardware accelerators (e.g., FPGAs, ASICs) for deep neural networks (DNNs) introduces new security vulnerabilities. Conventional model-level backdoor…
Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +2
Hardware Fuzzing emerged as one of the crucial techniques for finding security flaws in modern hardware designs by testing a wide range of input scenarios. One of the main challeng…
DASH: A Meta-Attack Framework for Synthesizing Effective and Stealthy Adversarial Examples
Abdullah Al Nomaan Nafi, Habibur Rahaman, Zafaryab Haider +4
Numerous techniques have been proposed for generating adversarial examples in white-box settings under strict Lp-norm constraints. However, such norm-bounded examples often fail to…
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Tanzim Mahfuz, Sudipta Paria, Tasneem Suha +2
Microelectronic systems are widely used in many sensitive applications (e.g., manufacturing, energy, defense). These systems increasingly handle sensitive data (e.g., encryption ke…
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
Kshitij Raj, Atri Chatterjee, Patanjali SLPSK +2
Designing secure architectures for system-on-chip (SoC) platforms is a highly intricate and time-intensive task, often requiring months of development and meticulous verification.…
Secure and Storage-Efficient Deep Learning Models for Edge AI Using Automatic Weight Generation
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
Complex neural networks require substantial memory to store a large number of synaptic weights. This work introduces WINGs (Automatic Weight Generator for Secure and Storage-Effici…
LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta +2
Ensuring the security of modern System-on-Chip (SoC) designs poses significant challenges due to increasing complexity and distributed assets across the intellectual property (IP)…
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta +2
Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D hetero…
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +3
In the evolving landscape of integrated circuit (IC) design, the increasing complexity of modern processors and intellectual property (IP) cores has introduced new challenges in en…
Runtime Detection of Adversarial Attacks in AI Accelerators Using Performance Counters
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
Rapid adoption of AI technologies raises several major security concerns, including the risks of adversarial perturbations, which threaten the confidentiality and integrity of AI a…
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection
Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha +2
Hardware Trojans are malicious modifications in digital designs that can be inserted by untrusted supply chain entities. Hardware Trojans can give rise to diverse attack vectors su…
Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection
Aritra Dasgupta, Sudipta Paria, Christopher Sozio +2
Existing countermeasures for hardware IP protection, such as obfuscation, camouflaging, and redaction, aim to defend against confidentiality and integrity attacks. However, within…