29 citations · 79 across the 45 of their papers we have counts for
12 papers · 1 filter
LEAN: Loss-Engineered Modulation of the Model Weight-Sensitivity Distribution for Efficient, Error-Tolerant Neural Networks
Habibur Rahaman, Swarup Bhunia
The weights of a trained network do not have uniform sensitivity to model accuracy: the 1% most sensitive weights carry about a fifth of the damage a bit flip can do. This distribu…
BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
Habibur Rahaman, Swastik Bhattacharya, Sanjay Das +2
Deep Neural Networks (DNNs) are integral to many safety critical systems, yet they remain highly vulnerable to bit-flip attacks (BFAs), where a few memory level perturbations can d…
CITADEL: CWE-Guided Insertion of Hardware Trojans via Analysis of DFG-Enabled LLMs
Jayanth Thangellamudi, Raghul Saravanan, Sudipta Paria +2
The increasing sophistication of Hardware Trojans (HTs) and system-level vulnerabilities poses significant risks to modern integrated circuits. However, constructing realistic HT s…
Security-Enhanced Seed-Based Weight Quantization for Large Language Models
Qiuyu Ren, Sudipta Paria, Aritra Dasgupta +1
Large language models (LLMs) incur substantial storage, memory-bandwidth and energy costs, motivating compact weight representations. Existing seed-based compression methods recons…
Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights
Sudipta Paria, Aritra Dasgupta, Raghul Saravanan +3
Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verifica…
(A)iSpy: Parasitic Trojans for Machine Learning Infrastructure
Habibur Rahaman, Qipan Xu, Zafaryab Haider +3
Modern machine learning (ML) pipelines depend heavily on third party libraries for graph compilation and hardware acceleration. While current practices audit data and model artifac…
An Automated Framework for Generating Stealthy Cell-Embedded Hardware Trojans
Raghul Saravanan, Sudipta Paria, Sai Manoj P D +1
Hardware Trojans (HTs) pose significant threats across the Integrated Circuit (IC) design lifecycle because they can be inserted by untrusted entities at different stages under the…
FrequencyFormer: A Co-Designed Sensor-to-Processor Pipeline for Frequency-Domain Vision Transformer Inference
Chengwei Zhou, Ovishake Sen, Xuming Chen +5
Deploying vision transformers (ViTs) on sensor-edge systems is limited not only by on-device compute, but also by the energy and bandwidth required to transmit high-dimensional ima…
Characterizing the Impact of NVFP4 Quantization for Low-Power Edge AI Deployment
Ovishake Sen, Venkata Nithin Kamineni, Daniel Lobo +3
Energy-efficient neural-network inference at the edge requires reducing arithmetic cost, memory traffic, computation energy, and storage overhead while maintaining acceptable accur…
LASH: Adaptive Semantic Hybridization for Black-Box Jailbreaking of Large Language Models
Abdullah Al Nomaan Nafi, Fnu Suya, Swarup Bhunia +1
Jailbreak attacks expose a persistent gap between the intended safety behavior of aligned large language models and their behavior under adversarial prompting. Existing automated m…
CIPHR: Cryptography Inspired IP Protection through Fine-Grain Hardware Redaction
Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
Hardware intellectual property (IP) in the globalized integrated circuit (IC) supply chain is exposed to a wide range of confidentiality and integrity attacks by untrusted third-pa…
COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
Mahmudul Hasan, Sudipta Paria, Swarup Bhunia +1
Commercial Off-The-Shelf (COTS) hardware, such as microprocessors, are widely adopted in system design due to their ability to reduce development time and cost compared to custom s…