29 citations · 68 across the 36 of their papers we have counts for
5 papers · 1 filter
Characterizing the Impact of NVFP4 Quantization for Low-Power Edge AI Deployment
Ovishake Sen, Venkata Nithin Kamineni, Daniel Lobo +3
Energy-efficient neural-network inference at the edge requires reducing arithmetic cost, memory traffic, computation energy, and storage overhead while maintaining acceptable accur…
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
Kshitij Raj, Atri Chatterjee, Patanjali SLPSK +2
Designing secure architectures for system-on-chip (SoC) platforms is a highly intricate and time-intensive task, often requiring months of development and meticulous verification.…
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta +2
Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D hetero…
Look-Up Table based Neural Network Hardware
Ovishake Sen, Chukwufumnanya Ogbogu, Peyman Dehghanzadeh +4
Traditional digital implementations of neural accelerators are limited by high power and area overheads, while analog and non-CMOS implementations suffer from noise, device mismatc…
LUNA-CIM: Lookup Table based Programmable Neural Processing in Memory
Peyman Dehghanzadeh, Baibhab Chatterjee, Swarup Bhunia
This paper presents a novel approach for performing computations using Look-Up Tables (LUTs) tailored specifically for Compute-in-Memory applications. The aim is to address the sca…