29 citations · 79 across the 45 of their papers we have counts for
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BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
Habibur Rahaman, Swastik Bhattacharya, Sanjay Das +2
Deep Neural Networks (DNNs) are integral to many safety critical systems, yet they remain highly vulnerable to bit-flip attacks (BFAs), where a few memory level perturbations can d…
CITADEL: CWE-Guided Insertion of Hardware Trojans via Analysis of DFG-Enabled LLMs
Jayanth Thangellamudi, Raghul Saravanan, Sudipta Paria +2
The increasing sophistication of Hardware Trojans (HTs) and system-level vulnerabilities poses significant risks to modern integrated circuits. However, constructing realistic HT s…
Security-Enhanced Seed-Based Weight Quantization for Large Language Models
Qiuyu Ren, Sudipta Paria, Aritra Dasgupta +1
Large language models (LLMs) incur substantial storage, memory-bandwidth and energy costs, motivating compact weight representations. Existing seed-based compression methods recons…
Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights
Sudipta Paria, Aritra Dasgupta, Raghul Saravanan +3
Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verifica…
(A)iSpy: Parasitic Trojans for Machine Learning Infrastructure
Habibur Rahaman, Qipan Xu, Zafaryab Haider +3
Modern machine learning (ML) pipelines depend heavily on third party libraries for graph compilation and hardware acceleration. While current practices audit data and model artifac…
An Automated Framework for Generating Stealthy Cell-Embedded Hardware Trojans
Raghul Saravanan, Sudipta Paria, Sai Manoj P D +1
Hardware Trojans (HTs) pose significant threats across the Integrated Circuit (IC) design lifecycle because they can be inserted by untrusted entities at different stages under the…
CIPHR: Cryptography Inspired IP Protection through Fine-Grain Hardware Redaction
Aritra Dasgupta, Sudipta Paria, Swarup Bhunia
Hardware intellectual property (IP) in the globalized integrated circuit (IC) supply chain is exposed to a wide range of confidentiality and integrity attacks by untrusted third-pa…
HAMLOCK: HArdware-Model LOgically Combined attacK
Sanskar Amgain, Daniel Lobo, Atri Chatterjee +2
The growing use of third-party hardware accelerators (e.g., FPGAs, ASICs) for deep neural networks (DNNs) introduces new security vulnerabilities. Conventional model-level backdoor…
Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +2
Hardware Fuzzing emerged as one of the crucial techniques for finding security flaws in modern hardware designs by testing a wide range of input scenarios. One of the main challeng…
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Tanzim Mahfuz, Sudipta Paria, Tasneem Suha +2
Microelectronic systems are widely used in many sensitive applications (e.g., manufacturing, energy, defense). These systems increasingly handle sensitive data (e.g., encryption ke…
LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation
Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta +2
Ensuring the security of modern System-on-Chip (SoC) designs poses significant challenges due to increasing complexity and distributed assets across the intellectual property (IP)…
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta +3
In the evolving landscape of integrated circuit (IC) design, the increasing complexity of modern processors and intellectual property (IP) cores has introduced new challenges in en…
Runtime Detection of Adversarial Attacks in AI Accelerators Using Performance Counters
Habibur Rahaman, Atri Chatterjee, Swarup Bhunia
Rapid adoption of AI technologies raises several major security concerns, including the risks of adversarial perturbations, which threaten the confidentiality and integrity of AI a…
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection
Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha +2
Hardware Trojans are malicious modifications in digital designs that can be inserted by untrusted supply chain entities. Hardware Trojans can give rise to diverse attack vectors su…
Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection
Aritra Dasgupta, Sudipta Paria, Christopher Sozio +2
Existing countermeasures for hardware IP protection, such as obfuscation, camouflaging, and redaction, aim to defend against confidentiality and integrity attacks. However, within…
X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration
Tanzim Mahfuz, Swarup Bhunia, Prabuddha Chakraborty
Design and manufacturing of integrated circuits predominantly use a globally distributed semiconductor supply chain involving diverse entities. The modern semiconductor supply chai…
DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia
Securing critical assets in a bus-based System-On-Chip (SoC) is imperative to mitigate potential vulnerabilities and prevent unauthorized access, ensuring the integrity, availabili…
DiSPEL: Distributed Security Policy Enforcement for Bus-based SoC
Sudipta Paria, Swarup Bhunia
The current zero trust model adopted in System-on-Chip (SoC) design is vulnerable to various malicious entities, and modern SoC designs must incorporate various security policies t…
Automatic Hardware Trojan Insertion using Machine Learning
Jonathan Cruz, Pravin Gaikwad, Abhishek Nair +2
Due to the current horizontal business model that promotes increasing reliance on untrusted third-party Intellectual Properties (IPs), CAD tools, and design facilities, hardware Tr…
Software Variants for Hardware Trojan Detection and Resilience in COTS Processors
Mahmudul Hasan, Jonathan Cruz, Prabuddha Chakraborty +2
The commercial off-the-shelf (COTS) component based ecosystem provides an attractive system design paradigm due to the drastic reduction in development time and cost compared to cu…
Third-Party Hardware IP Assurance against Trojans through Supervised Learning and Post-processing
Pravin Gaikwad, Jonathan Cruz, Prabuddha Chakraborty +2
System-on-chip (SoC) developers increasingly rely on pre-verified hardware intellectual property (IP) blocks acquired from untrusted third-party vendors. These IPs might contain hi…
MeLPUF: Memory-in-Logic PUF Structures for Low-Overhead IC Authentication
Christopher Vega, Shubhra Deb Paul, Patanjali SLPSK +1
Physically Unclonable Functions (PUFs) are used for securing electronic devices across the implementation spectrum ranging from Field Programmable Gate Array (FPGA) to system on ch…
Scalable Attack-Resistant Obfuscation of Logic Circuits
Abdulrahman Alaql, Swarup Bhunia
Hardware IP protection has been one of the most critical areas of research in the past years. Recently, attacks on hardware IPs (such as reverse engineering or cloning) have evolve…
SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection
Abhishek Nair, Patanjali SLPSK, Chester Rebeiro +1
The emergence of distributed manufacturing ecosystems for electronic hardware involving untrusted parties has given rise to diverse trust issues. In particular, IP piracy, overprod…