A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

Abstract

High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offered by numerous compilers (e.g., MLIR, TVM, OpenXLA), performance-critical micro-kernels are left to specialized code generators or handwritten assembly. Even though widely-adopted compilers (e.g., LLVM, GCC) offer tuned backends, their CPU-focused input abstraction, unstructured IR, and general-purpose best-effort design inhibit tailored code generation for innovative hardware. We think it is time to widen the classical hourglass backend and embrace progressive lowering across a diverse set of structured abstractions to bring domain-specific code generation to compiler backends. We demonstrate this concept by implementing a custom backend for a RISC-V-based accelerator with hardware loops and streaming registers, leveraging knowledge about the hardware at levels of abstraction that match its custom ISA. We use incremental register allocation over structured IRs, while dropping classical spilling heuristics, and show up to 90% FPU utilization across key DNN kernels. By breaking the backend hourglass model, we reopen the path from domain-specific abstractions to specialized hardware.

References in corpus (7)

• Learning to Optimize Tensor Programs
• Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
• Analytical Characterization and Design Space Exploration for Optimization of CNNs
• Compiling ONNX Neural Network Models Using MLIR
• A shared compilation stack for distributed-memory parallelism in stencil DSLs
• Fast Matrix Multiplication via Compiler-only Layered Data Reorganization and Intrinsic Lowering
• Sidekick compilation with xDSL