46 citations · 61 across the 14 of their papers we have counts for
17 papers
CONFERM: Recurrence-Aware Temporal Mapping for Multi-Cycle Multi-Context CGRAs
Jun Yin, Jannes Willemen, Stef Cuyckens +2
Throughput in DSP and machine learning workloads is often limited by two temporal structures, i.e., loop-carried recurrences and long-latency, multi-cycle compute nodes. On spatio-…
ShatterQuant: Breaking Uniform Precision with Block-Wise Mixed-Precision on a Systolic Transformer Hardware Accelerator
Mikolaj Walczak, Edward Humes, Chao Fang +2
Due to limited support for intra-tensor heterogeneous precision in conventional accelerators, neural network quantization remains largely restricted to per-tensor precision assignm…
ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents
Stef Cuyckens, Mihaela Jivanescu, Jun Yin +2
Large language model (LLM) agents optimize the power, performance, and area (PPA) of register-transfer-level (RTL) designs by iterating over edits, synthesis, and PPA analysis, pay…
HiKV: Hierarchical Importance-Aware KV Cache with Hardware Acceleration for LLM Decoding
Chao Fang, Jun Yin, Man Shi +1
With the rapid adoption of long-context large language models (LLMs), the continuously growing KV cache during decoding has become the critical memory bottleneck. To tackle this ch…
TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware
Jonas Crols, Guilherme Paim, Shirui Zhao +1
Bayesian Neural Networks (BNNs) offer opportunities for greatly enhancing the trustworthiness of conventional neural networks by monitoring the uncertainties in decision-making. A…
A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
Xiaoling Yi, Ryan Antonio, Yunhao Deng +4
Achieving high compute utilization across a wide range of AI workloads is crucial for the efficiency of versatile DNN accelerators. This paper presents the Voltra chip and its util…
Torrent: A Distributed DMA for Efficient and Flexible Point-to-Multipoint Data Movement
Yunhao Deng, Fanchen Kong, Xiaoling Yi +2
The growing disparity between computational power and on-chip communication bandwidth is a critical bottleneck in modern Systems-on-Chip (SoCs), especially for data-parallel worklo…
The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead
Josse Van Delm, Anton Lydike, Joren Dumoulin +6
Contemporary compute platforms increasingly offload compute kernels from CPU to integrated hardware accelerators to reach maximum performance per Watt. Unfortunately, the time the…
Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration
Stef Cuyckens, Xiaoling Yi, Robin Geens +4
Emerging continual learning applications necessitate next-generation neural processing unit (NPU) platforms to support both training and inference operations. The promising Microsc…
P3-LLM: An Integrated NPU-PIM Accelerator for Edge LLM Inference Using Hybrid Numerical Formats
Yuzong Chen, Chao Fang, Xilai Dai +4
The substantial memory bandwidth and computational demands of large language models (LLMs) present critical challenges for efficient inference. To tackle this, the literature has e…
iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator
Stef Cuyckens, Ryan Antonio, Chao Fang +1
Implantable devices for reliable intracranial electroencephalography (iEEG) require efficient, accurate, and real-time detection of seizures. Dense hyperdimensional computing (HDC)…
An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems
Ryan Albert Antonio, Joren Dumoulin, Xiaoling Yi +4
Heterogeneous accelerator-centric compute clusters are emerging as efficient solutions for diverse AI workloads. However, current integration strategies often compromise data movem…
XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCs
Fanchen Kong, Yunhao Deng, Xiaoling Yi +2
As modern AI workloads increasingly rely on heterogeneous accelerators, ensuring high-bandwidth and layout-flexible data movements between accelerator memories has become a pressin…
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration
Man Shi, Vikram Jain, Antony Joseph +2
Bit-serial computation facilitates bit-wise sequential data processing, offering numerous benefits, such as a reduced area footprint and dynamically-adaptive computational precisio…
DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators
Xiaoling Yi, Yunhao Deng, Ryan Antonio +3
Deep Neural Networks (DNNs) have achieved remarkable success across various intelligent tasks but encounter performance and energy challenges in inference execution due to data mov…
A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions
Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis +6
High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offere…
OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling
Xiaoling Yi, Ryan Antonio, Joren Dumoulin +4
Deep neural networks (DNNs) face significant challenges when deployed on resource-constrained extreme edge devices due to their computational and data-intensive nature. While stand…