32 citations · 62 across the 18 of their papers we have counts for
20 papers
STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications
Jun Yin, Chao Fang, Ryan Antonio +4
Emerging non-matrix ML kernels, such as LayerNorm, GeLu, FFT or circular convolutions, demand low-latency, energy-efficient spatial accelerators beyond MatMul-centric arrays. STELL…
A 25-s/inf Event-driven Graph Neural Network Processor with Spatiotemporal Caching and Spline Convolution for Ultra-low-latency AI at the Edge
Adrian Kneip, Martin Lefebvre, Daniel Gehrig +4
Dynamic-vision-sensor (DVS) cameras generate events on a per-pixel basis with a s-level temporal resolution, calling for new algorithm-hardware co-design approaches compared to…
ETHEREAL: A 25.6-s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge
Adrian Kneip, Martin Lefebvre, Daniel Gehrig +4
Dynamic vision sensors (DVS) are enticing candidates to reach the low-latency, sub-ms target of edge-vision applications, as they generate events with a s-level time resolution.…
AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing
Shirui Zhao, Nimish Shah, Wannes Meert +1
Probabilistic graphical models (PMs) are popular to empower machine learning with the ability of reasoning and decision-making. To perform approximate inference in PMs, sampling-ba…
Agent Memory: Characterization and System Implications of Stateful Long-Horizon Workloads
Yasmine Omri, Ziyu Gan, Zachary Broveak +6
LLM agents are increasingly deployed on long-horizon tasks requiring sustained reasoning over extended interaction histories. Realizing this at scale requires agents to persistentl…
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
Robin Geens, Joran Heldens, Joren Dumoulin +1
Ternary weight quantization (e.g., BitNet b1.58) offers a promising path to mitigate the memory bandwidth bottleneck in Large Language Model (LLM) inference. However, conventional…
The Hyperscale Lottery: How State-Space Models Have Sacrificed Edge Efficiency
Robin Geens, Jonas De Schouwer, Marian Verhelst +1
The Hardware Lottery posits that research directions are dictated by available silicon compute platforms. We identify a derivative phenomenon, the Hyperscale Lottery, where model a…
MONET: Modeling and Optimization of neural NEtwork Training from Edge to Data Centers
Jérémy Morlier, Robin Geens, Stef Cuyckens +4
While hardware-software co-design has significantly improved the efficiency of neural network inference, modeling the training phase remains a critical yet underexplored challenge.…
Hardware-Algorithm Co-Optimization of Early-Exit Neural Networks for Multi-Core Edge Accelerators
Alaa Zniber, Arne Symons, Ouassim Karrakchou +2
The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also its hardware deployment. Exit configurat…
Decoupled Control Flow and Data Access in RISC-V GPGPUs
Giuseppe M. Sarda, Nimish Shah, Abubakr Nada +2
Vortex, a newly proposed open-source GPGPU platform based on the RISC-V ISA, offers a valid alternative for GPGPU research over the broadly-used modeling platforms based on commerc…
Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention
Robin Geens, Marian Verhelst
Multi-Head Latent Attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key, and value tensors into a compact latent spa…
Fine-Grained Fusion: The Missing Piece in Area-Efficient State Space Model Acceleration
Robin Geens, Arne Symons, Marian Verhelst
State Space Models (SSMs) offer a promising alternative to transformers for long-sequence processing. However, their efficiency remains hindered by memory-bound operations, particu…
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
Chao Fang, Man Shi, Robin Geens +3
The widely-used, weight-only quantized large language models (LLMs), which leverage low-bit integer (INT) weights and retain floating-point (FP) activations, reduce storage require…
MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices
Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda +6
Streamlining the deployment of Deep Neural Networks (DNNs) on heterogeneous edge platforms, coupling within the same micro-controller unit (MCU) instruction processors and hardware…
Pack my weights and run! Minimizing overheads for in-memory computing accelerators
Pouya Houshmand, Marian Verhelst
In-memory computing hardware accelerators allow more than 10x improvements in peak efficiency and performance for matrix-vector multiplications (MVM) compared to conventional digit…
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis
Giuseppe M. Sarda, Nimish Shah, Debjyoti Bhattacharjee +2
GPGPU execution analysis has always been tied to closed-source, proprietary benchmarking tools that provide high-level, non-exhaustive, and/or statistical information, preventing a…
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
Steven Colleman, Arne Symons, Victor J. B. Jung +1
The impact of transformer networks is booming, yet, they come with significant computational complexity. It is therefore essential to understand how to optimally map and execute th…
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Josse Van Delm, Maarten Vandersteegen, Alessio Burrello +5
Optimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these SoC…
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators
Jun Yin, Linyan Mei, Andre Guntoro +1
Spatio-Temporal Convolutional Neural Networks (ST-CNN) allow extending CNN capabilities from image processing to consecutive temporal-pattern recognition. Generally, state-of-the-a…
Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling
Jiacong Sun, Pouya Houshmand, Marian Verhelst
In-Memory Computing (IMC) has emerged as a promising paradigm for energy-efficient, throughput-efficient and area-efficient machine learning at the edge. However, the differences i…