32 citations · 62 across the 18 of their papers we have counts for
8 papers · 1 filter
STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications
Jun Yin, Chao Fang, Ryan Antonio +4
Emerging non-matrix ML kernels, such as LayerNorm, GeLu, FFT or circular convolutions, demand low-latency, energy-efficient spatial accelerators beyond MatMul-centric arrays. STELL…
A 25-s/inf Event-driven Graph Neural Network Processor with Spatiotemporal Caching and Spline Convolution for Ultra-low-latency AI at the Edge
Adrian Kneip, Martin Lefebvre, Daniel Gehrig +4
Dynamic-vision-sensor (DVS) cameras generate events on a per-pixel basis with a s-level temporal resolution, calling for new algorithm-hardware co-design approaches compared to…
ETHEREAL: A 25.6-s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge
Adrian Kneip, Martin Lefebvre, Daniel Gehrig +4
Dynamic vision sensors (DVS) are enticing candidates to reach the low-latency, sub-ms target of edge-vision applications, as they generate events with a s-level time resolution.…
AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing
Shirui Zhao, Nimish Shah, Wannes Meert +1
Probabilistic graphical models (PMs) are popular to empower machine learning with the ability of reasoning and decision-making. To perform approximate inference in PMs, sampling-ba…
Agent Memory: Characterization and System Implications of Stateful Long-Horizon Workloads
Yasmine Omri, Ziyu Gan, Zachary Broveak +6
LLM agents are increasingly deployed on long-horizon tasks requiring sustained reasoning over extended interaction histories. Realizing this at scale requires agents to persistentl…
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
Robin Geens, Joran Heldens, Joren Dumoulin +1
Ternary weight quantization (e.g., BitNet b1.58) offers a promising path to mitigate the memory bandwidth bottleneck in Large Language Model (LLM) inference. However, conventional…
The Hyperscale Lottery: How State-Space Models Have Sacrificed Edge Efficiency
Robin Geens, Jonas De Schouwer, Marian Verhelst +1
The Hardware Lottery posits that research directions are dictated by available silicon compute platforms. We identify a derivative phenomenon, the Hyperscale Lottery, where model a…
MONET: Modeling and Optimization of neural NEtwork Training from Edge to Data Centers
Jérémy Morlier, Robin Geens, Stef Cuyckens +4
While hardware-software co-design has significantly improved the efficiency of neural network inference, modeling the training phase remains a critical yet underexplored challenge.…