activity
20232026
most citedA Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

9 citations · 17 across the 6 of their papers we have counts for

collaborators

7 papers

cs.DC2026

An MLIR Lowering Pipeline for Stencils at Wafer-Scale

Nicolai Stawinoga, David Katz, Anton Lydike +4

The Cerebras Wafer-Scale Engine (WSE) delivers performance at an unprecedented scale of over 900,000 compute units, all connected via a single-wafer on-chip interconnect. Initially…

cs.PF2025

The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead

Josse Van Delm, Anton Lydike, Joren Dumoulin +6

Contemporary compute platforms increasingly offload compute kernels from CPU to integrated hardware accelerators to reach maximum performance per Watt. Unfortunately, the time the…

cs.PL2025★ 9 cited

A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis +6

High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offere…

cs.PL2024★ 1 cited

Compressing Structured Tensor Algebra

Mahdi Ghorbani, Emilien Bauer, Tobias Grosser +1

Tensor algebra is a crucial component for data-intensive workloads such as machine learning and scientific computing. As the complexity of data grows, scientists often encounter a…

cs.PL2023

mlirSynth: Automatic, Retargetable Program Raising in Multi-Level IR using Program Synthesis

Alexander Brauckmann, Elizabeth Polgreen, Tobias Grosser +1

MLIR is an emerging compiler infrastructure for modern hardware, but existing programs cannot take advantage of MLIR's high-performance compilation if they are described in lower-l…

cs.DC2023

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA

Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson +3

The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technolo…

cs.DC2023★ 7 cited

Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang

Nick Brown, Maurice Jamieson, Anton Lydike +2

MLIR has become popular since it was open sourced in 2019. A sub-project of LLVM, the flexibility provided by MLIR to represent Intermediate Representations (IR) as dialects at dif…