High-Density Superconductive Logic Circuits Utilizing 0 and Josephson Junctions
arXiv:2308.12474 · doi:10.1088/2631-8695/ad27f5
Abstract
Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the primary challenge confronting SCE today pertains to its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay is about 4ps while maintaining over 50% parameter margins. This logic is power efficient and can increase the integration by at least 100 in the SCE chips.
arXiv comment9 pages, 16 figures
References in corpus (9)
- Coupling of two superconductors through a ferromagnet : evidence for a pi-junction
- Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
- Josephson junctions with negative second harmonic in the current-phase relation: properties of novel varphi-junctions
- Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits
- Second-harmonic current-phase relation in Josephson junctions with ferromagnetic barriers
- Method for reliable realization of a varphi Josephson junction
- Superconducting circuits without inductors based on bistable Josephson junctions
- Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions
- A Hybrid Josephson Transmission Line and Passive Transmission Line Routing Framework for Single Flux Quantum Logic