82 citations · 321 across the 33 of their papers we have counts for
38 papers
Design of a Superconducting Multiflux Non-Destructive Readout Memory Unit
Beyza Zeynep Ucpinar, Yasemin Kopur, Mustafa Altay Karamuftuoglu +2
Due to low power consumption and high-speed performance, superconductor circuit technology has emerged as an attractive and compelling post-CMOS technology candidate. However, the…
High-Density Superconductive Logic Circuits Utilizing 0 and Josephson Junctions
Sasan Razmkhah, Massoud Pedram
Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the prima…
A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits
Masoud Zabihi, Yanyue Xie, Zhengang Li +5
The production process of superconductive integrated circuits is complex and consumes significant amounts of resources and energy. Therefore, it is crucial to evaluate the environm…
HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise
Souvik Kundu, Massoud Pedram, Peter A. Beerel
Low-latency deep spiking neural networks (SNNs) have become a promising alternative to conventional artificial neural networks (ANNs) because of their potential for increased energ…
Towards Low-Latency Energy-Efficient Deep SNNs via Attention-Guided Compression
Souvik Kundu, Gourav Datta, Massoud Pedram +1
Deep spiking neural networks (SNNs) have emerged as a potential alternative to traditional deep learning frameworks, due to their promise to provide increased compute efficiency on…
Coarse2Fine: A Two-stage Training Method for Fine-grained Visual Classification
Amir Erfan Eshratifar, David Eigen, Michael Gormish +1
Small inter-class and large intra-class variations are the main challenges in fine-grained visual classification. Objects from different classes share visually similar structures a…
Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework
Ting-Ru Lin, Drew Penney, Massoud Pedram +1
Machine learning applied to architecture design presents a promising opportunity with broad applications. Recent deep reinforcement learning (DRL) techniques, in particular, enable…
Energy-Aware Scheduling of Task Graphs with Imprecise Computations and End-to-End Deadlines
Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram
Imprecise computations provide an avenue for scheduling algorithms developed for energy-constrained computing devices by trading off output quality with the utilization of system r…
VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology
Alvin D. Wong, Kevin Su, Hang Sun +3
In this paper, we propose a semi-formal verification framework for single-flux quantum (SFQ) circuits called VeriSFQ, using the Universal Verification Methodology (UVM) standard. T…
BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services
Amir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram
Recent studies have shown the latency and energy consumption of deep neural networks can be significantly improved by splitting the network between the mobile device and cloud. Thi…
Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays
Ghasem Pasandi, Raghav Mehta, Massoud Pedram +1
Memory accounts for a considerable portion of the total power budget and area of digital systems. Furthermore, it is typically the performance bottleneck of the processing units. T…
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
Ghasem Pasandi, Shahin Nazarian, Massoud Pedram
Approximate Logic Synthesis (ALS) is the process of synthesizing and mapping a given Boolean network to a library of logic cells so that the magnitude/rate of error between outputs…
Towards Collaborative Intelligence Friendly Architectures for Deep Learning
Amir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram
Modern mobile devices are equipped with high-performance hardware resources such as graphics processing units (GPUs), making the end-side intelligent services more feasible. Even r…
SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits
Ghasem Pasandi, Alireza Shafaei, Massoud Pedram
Single flux quantum (SFQ) logic is a promising candidate to replace the CMOS logic for high speed and low power applications due to its superiority in providing high performance an…
PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits
Ghasem Pasandi, Massoud Pedram
This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logi…
Space Expansion of Feature Selection for Designing more Accurate Error Predictors
Shayan Tabatabaei Nikkhah, Mehdi Kamal, Ali Afzali-Kusha +1
Approximate computing is being considered as a promising design paradigm to overcome the energy and performance challenges in computationally demanding applications. If the case wh…
Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline
Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram
Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DV…
Gradient Agreement as an Optimization Objective for Meta-Learning
Amir Erfan Eshratifar, David Eigen, Massoud Pedram
This paper presents a novel optimization method for maximizing generalization over tasks in meta-learning. The goal of meta-learning is to learn a model for an agent adapting rapid…
A Graph Partitioning Algorithm with Application in Synthesizing Single Flux Quantum Logic Circuits
Ghasem Pasandi, Massoud Pedram
In this paper, a new graph partitioning problem is introduced. The depth of each part is constrained, i.e., the node count in the longest path of the corresponding sub-graph is no…
SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application
Arash Fayyazi, Souvik Kundu, Shahin Nazarian +2
In this paper, we propose an efficient predefined structured sparsity-based ex-situ training framework for a hybrid CMOS-memristive neuromorphic hardware for deep neural network to…
A Meta-Learning Approach for Custom Model Training
Amir Erfan Eshratifar, Mohammad Saeed Abrishami, David Eigen +1
Transfer-learning and meta-learning are two effective methods to apply knowledge learned from large data sources to new tasks. In few-class, few-shot target task settings (i.e. whe…
NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference
Mahdi Nazemi, Ghasem Pasandi, Massoud Pedram
Deep neural networks have been successfully deployed in a wide variety of applications including computer vision and speech recognition. However, computational and storage complexi…
Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications
Mahdi Nazemi, Massoud Pedram
Major advancements in building general-purpose and customized hardware have been one of the key enablers of versatility and pervasiveness of machine learning models such as deep ne…
VIBNN: Hardware Acceleration of Bayesian Neural Networks
Ruizhe Cai, Ao Ren, Ning Liu +5
Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probabi…