Gating of high-mobility InAs metamorphic heterostructures

Abstract

We investigate the performance of gate-defined devices fabricated on high mobility InAs metamorphic heterostructures. We find that heterostructures capped with In${}_{0.75}$Ga${}_{0.25}$As often show signs of parallel conduction due to proximity of their surface Fermi level to the conduction band minimum. Here, we introduce a technique that can be used to estimate the density of this surface charge that involves cool-downs from room temperature under gate bias. We have been able to remove the parallel conduction under high positive bias, but achieving full depletion has proven difficult. We find that by using In${}_{0.75}$Al${}_{0.25}$As as the barrier without an In${}_{0.75}$Ga${}_{0.25}$As capping, a drastic reduction in parallel conduction can be achieved. Our studies show that this does not change the transport properties of the quantum well significantly. We achieved full depletion in InAlAs capped heterostructures with non-hysteretic gating response suitable for fabrication of gate-defined mesoscopic devices.

References in corpus (1)

• An apparent metal insulator transition in high mobility 2D InAs heterostructures

Cited by in corpus (4)

• Progress in superconductor-semiconductor topological Josephson junctions
• Observation of fractional quantum Hall effect in an InAs quantum well
• Magnetic Field Inducing Zeeman Splitting and Anomalous Conductance Reduction of Half-integer Quantized Plateaus in InAs Quantum Wires
• Clean quantum point contacts in an InAs quantum well grown on a lattice-mismatched InP substrate