Implanted Bottom Gate for Epitaxial Graphene on Silicon Carbide

Abstract

We present a technique to tune the charge density of epitaxial graphene via an electrostatic gate that is buried in the silicon carbide substrate. The result is a device in which graphene remains accessible for further manipulation or investigation. Via nitrogen or phosphor implantation into a silicon carbide wafer and subsequent graphene growth, devices can routinely be fabricated using standard semiconductor technology. We have optimized samples for room temperature as well as for cryogenic temperature operation. Depending on implantation dose and temperature we operate in two gating regimes. In the first, the gating mechanism is similar to a MOSFET, the second is based on a tuned space charge region of the silicon carbide semiconductor. We present a detailed model that describes the two gating regimes and the transition in between.

Manuscript submitted to Journal of Physics D

References in corpus (8)

• The Raman Fingerprint of Graphene
• Ultrahigh electron mobility in suspended graphene
• Detection of Individual Gas Molecules Absorbed on Graphene
• Boron nitride substrates for high-quality graphene electronics
• Ultrathin epitaxial graphite: 2D electron gas properties and a route toward graphene-based nanoelectronics
• Energy gaps in etched graphene nanoribbons
• The quasi-free-standing nature of graphene on H-saturated SiC(0001)
• How Graphene-like is Epitaxial Graphene? \\Quantum Oscillations and Quantum Hall Effect