Simulations of gated Si nanowires and 3-nm junctionless transistors

Abstract

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ~1 nm wire diameter and ~3 nm gate length, and that the junctionless transistor may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.

References in corpus (2)

• Deformation Potentials and Electron-Phonon Coupling in Silicon Nanowires
• Ballistic Conductance in Oxidized Si Nanowires

Cited by in corpus (4)

• First Principle-based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors
• Transport properties and electrical device characteristics with the TiMeS computational platform: application in silicon nanowires
• Effect of strain and diameter on electronic and charge transport properties of indium arsenide nanowires
• New Multi-Scale Simulation Framework for Next-Generation Electronic Design Automation with Application to the Junctionless Transistor