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20122023
most citedAdvanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

253 citations · 628 across the 7 of their papers we have counts for

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cond-mat.supr-con2023★ 27 cited

Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

Sergey K. Tolpygo, Justin L. Mallek, Vladimir Bolkhovsky +5

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of Josephson junctions (JJs) per chip, we developed a new fabricat…

cond-mat.supr-con2021★ 14 cited

Wafer-Scale Characterization of a Superconductor Integrated Circuit Fabrication Process, Using a Cryogenic Wafer Prober

Joshua T. West, Arthur Kurlej, Alex Wynn +3

Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including…

cond-mat.supr-con2016★ 84 cited

Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2

Sergey K. Tolpygo, Vladimir Bolkhovsky, Scott Zarr +5

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their ba…

cond-mat.supr-con2015★ 253 cited

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

Sergey K. Tolpygo, Vladimir Bolkhovsky, T. J. Weir +4

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ)…

cond-mat.supr-con2014★ 172 cited

Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits

Sergey K. Tolpygo, Vladimir Bolkhovsky, Terence J. Weir +3

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is…

cond-mat.supr-con2014★ 77 cited

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers

Sergey K. Tolpygo, Vladimir Bolkhovsky, T. J. Weir +4

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and micro…

cond-mat.supr-con2012★ 1 cited

Shadow evaporation of epitaxial Al/Al2O3/Al tunnel junctions on sapphire utilizing an inorganic bilayer mask

Paul B. Welander, Vladimir Bolkhovsky, Terence J. Weir +2

This letter describes a new inorganic shadow mask that has been employed for the evaporation of all-epitaxial Al/Al2O3/Al superconducting tunnel junctions. Organic resists that are…