21 citations · 25 across the 18 of their papers we have counts for
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cs.AR2025
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Chengxi Li, Yang Sun, Lei Chen +3
This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…
cs.AR2024★ 1 cited
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Xufeng Yao, Yiwen Wang, Xing Li +6
Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization r…
cs.AR2024★ 21 cited
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
Lei Chen, Yiqi Chen, Zhufei Chu +36
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies.…