1 citations · 2 across the 12 of their papers we have counts for
16 papers
Self-Evolving Algorithm-Design Agents: Escaping In-Context Evolutionary Stagnation via Population-Curated Policy Optimization
Chen Lu, Ke Xue, Siyuan Xu +2
Large language models are increasingly participating in complex real-world tasks in the form of algorithm-design agents, designing and refining algorithms. Many successful algorith…
Focus Is All You Need: Adaptive Goal-aware Attention Orchestration for Multi-Agent Graph Systems
Mingzhou Fan, Siyuan Xu, Mingxuan Yuan
Large language models (LLMs) enable autonomous agents for reasoning, planning, and tool use. Recent systems increasingly organize these agents as graphs of specialized, interconnec…
How Can Reinforcement Learning Achieve Expert-level Placement?
Ruo-Tong Chen, Ke Xue, Chengrui Gao +7
Chip placement is a critical step in physical design. While reinforcement learning (RL)-based methods have recently emerged, their training primarily focuses on wirelength optimiza…
FlowPlace: Flow Matching for Chip Placement
Peng Xie, Ke Xue, Yunqi Shi +6
Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the followin…
Advancing Automated Algorithm Design via Evolutionary Stagewise Design with LLMs
Chen Lu, Ke Xue, Chengrui Gao +5
With the rapid advancement of human science and technology, problems in industrial scenarios are becoming increasingly challenging, bringing significant challenges to traditional a…
ReMaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating
Yunqi Shi, Xi Lin, Zhiang Wang +8
This work introduces the ReMaP method, which generates expert-quality macro placements through recursively prototyping and packing tree-based relocating. We first perf…
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
Ke Xue, Ruo-Tong Chen, Rong-Xi Tan +5
Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature pro…
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Zhexuan Xu, Kexin Zhou, Jie Wang +5
Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of…
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
Zhexuan Xu, Jie Wang, Siyuan Xu +3
Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However…
HyperTree Planning: Enhancing LLM Reasoning via Hierarchical Thinking
Runquan Gui, Zhihai Wang, Jie Wang +7
Recent advancements have significantly enhanced the performance of large language models (LLMs) in tackling complex reasoning tasks, achieving notable success in domains like mathe…
Accelerating Large Language Model Reasoning via Speculative Search
Zhihai Wang, Jie Wang, Jilai Pan +5
Tree-search-based reasoning methods have significantly enhanced the reasoning capability of large language models (LLMs) by facilitating the exploration of multiple intermediate re…
Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
Yunqi Shi, Chengrui Gao, Wanqi Ren +6
This work introduces Open3DBench, an open-source 3D-IC backend implementation benchmark built upon the OpenROAD-flow-scripts framework, enabling comprehensive evaluation of power,…
Timing-Driven Global Placement by Efficient Critical Path Extraction
Yunqi Shi, Siyuan Xu, Shixiong Kai +4
Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical metho…
E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction
Saurabh Bodhe, Zhanguang Zhang, Atia Hamidizadeh +3
Pre-routing slack prediction remains a critical area of research in Electronic Design Automation (EDA). Despite numerous machine learning-based approaches targeting this task, ther…
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
Zhihai Wang, Zijie Geng, Zhaojie Tu +12
The increasing complexity of modern very-large-scale integration (VLSI) design highlights the significance of Electronic Design Automation (EDA) technologies. Chip placement is a c…